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AD9371 Deframer FIFO depth adjust

Hi

On our customized board, we got the deframer fifo depth.
The FIFO depth is indicated the 30, 31, 32.

I think it is not good because it is FIFO depth boundary.

We changed the LMFC offset value on initdata.c however deframer fifo depth was not changed.

* LMFC = 0 : FIFO depth 30,31,32
* LMFC = 20 : FIFO depth 30,31,32

We want to know how to adjust the deframer fifo dpeth.

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  • We had changed the LMFC offset value on myk.c file.

    - Case : LMFC=0

    static mykonosJesd204bDeframerConfig_t deframer =
    {
        0,              /* bankId extension to Device ID (Valid 0..15)*/
        0,              /* deviceId  link identification number. (Valid 0..255)*/
        0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
        4,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
        32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
        1,              /* scramble  scrambling off if scramble= 0.*/
        1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
        0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
        0x04,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
        1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
        0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
        0,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
        0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
        0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
        0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
        0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
    };

    - Case : LMFC=20

    static mykonosJesd204bDeframerConfig_t deframer =
    {
        0,              /* bankId extension to Device ID (Valid 0..15)*/
        0,              /* deviceId  link identification number. (Valid 0..255)*/
        0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
        4,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
        32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
        1,              /* scramble  scrambling off if scramble= 0.*/
        1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
        0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
        0x04,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
        1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
        0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
        20,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
        0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
        0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
        0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
        0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
    };

  • Can you change the LMFC offset in the framer of the FPGA and then check the deframer FIFO depth of the AD9371 chip? Check if the FIFO depth is varying or not with the LMFC offset.

    Refer to the below link:

    https://ez.analog.com/fpga/f/q-a/165709/ad9371-does-lane-latency-confirm-the-deterministic-latency-exist-or-not/383312#383312