AD9371 Deframer FIFO depth adjust

Are you facing any performance issues? If the FIFO depth varies by 1 or 2 samples with every boot up, it should not affect. Hope you are not changing the LMFC offset in runtime as that might give sysref alignment error.  You need to initialize the board with the new LMFC offset value.

I think the FIFO is 32.
It is needed to changing for deterministic latency.

The FIFO depth of 32 looks good since the FIFO depth is 127 and the value is not close to both the boundaries.. 

From UG:

When establishing a JESD204B link, it is desirable that the data arriving to the deframer does not arrive very close to an LMFC boundary. If this does happen, the deterministic latency can vary from system to system if the data on one system arrives just before an LMFC event, and arrives on another system just after an LMFC event. If this happens, there is an LMFC period difference in the latency between the systems. Furthermore, the architecture in the device does not support a very small delay through the FIFO, and data corruption occurs if the delay is too small. Therefore, it is important that the FIFO depth be checked after the link is established, and the link is adjusted to achieve a FIFO depth that is close to the medium depth.

Sorry, we misunderstood about the FIFO depth.

Could you please tell me just for my reference how does the fifo depth change?

The FIFO depth depends on the LMFC offset parameter. If you increase the LMFC offset by 1, then the FIFO depth can either increase by 1 or decrease by 1. So in this way, if you keep on keep on varying the LMFC offset value, then you will be able to achieve a FIFO depth that is in the medium depth value. 

The FIFO depth depends on the LMFC offset parameter. If you increase the LMFC offset by 1, then the FIFO depth can either increase by 1 or decrease by 1. So in this way, if you keep on keep on varying the LMFC offset value, then you will be able to achieve a FIFO depth that is in the medium depth value. 

Thank you for quick response.

However, we can not change the FIFO depth when the LMFC value is changed.
We want to know how does the FIFO depth is change and how do we get the LMFC offset value?

How are you changing the LMFC value? Are you initializing the chip everytime you are changing the LMFC offset value?

We had changed the LMFC offset value on myk.c file.

- Case : LMFC=0

static mykonosJesd204bDeframerConfig_t deframer =
{
    0,              /* bankId extension to Device ID (Valid 0..15)*/
    0,              /* deviceId  link identification number. (Valid 0..255)*/
    0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
    4,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
    32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scramble  scrambling off if scramble= 0.*/
    1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
    0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
    0x04,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
    1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
    0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
    0,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
};

- Case : LMFC=20

static mykonosJesd204bDeframerConfig_t deframer =
{
    0,              /* bankId extension to Device ID (Valid 0..15)*/
    0,              /* deviceId  link identification number. (Valid 0..255)*/
    0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
    4,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
    32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scramble  scrambling off if scramble= 0.*/
    1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
    0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
    0x04,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
    1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
    0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
    20,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
};

Can you change the LMFC offset in the framer of the FPGA and then check the deframer FIFO depth of the AD9371 chip? Check if the FIFO depth is varying or not with the LMFC offset.

Refer to the below link:

https://ez.analog.com/fpga/f/q-a/165709/ad9371-does-lane-latency-confirm-the-deterministic-latency-exist-or-not/383312#383312