AD9371: TX LO leakage and Image problem

Hello all,

I have AD9371 IC with Zynq ultrascale plus MPSoC on the custom board.

While checking BIST tone, I am getting spectrum like this

LO frequency is at 2345 MHz (check marker 2)
The main frequency is 2348 MHz. (marker no. 1) and its image is shown by marker by 3.


I have observed LO frequency at 100KHz span. So it seems like it is not locking at one frequency.
Please give suggestions.

  • 0
    •  Analog Employees 
    on Jul 29, 2021 9:21 AM

    Check for PLL lock status using  MYKONOS_checkPllsLockStatus() 

    This function updates the pllLockStatus pointer with a lock status it per PLL. pllLockStatus[0] = CLKPLL Locked pllLockStatus[1] = RX_PLL Locked pllLockStatus[2] = TX_PLL Locked pllLockStatus[3] = SNIFFER_PLL Locked pllLockStatus[4] = CAL_PLL Locked

    What is the reference clock frequency given ? Is the reference clock locked and stable. ?
    Is the reference clock frequency matching with the device clock frequency in you init files ? 
    Make sure you run LOL and QEC cal for best performance . 
  • Hi Vinod,

    I have modified the ad9371.c file. And I have added code to check the lock status

    ret = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus);
        dev_err(&phy->spi->dev, "Checking MYKONOS_checkPllsLockStatus ret value: %s (%d) and pllLockStatus value : (%d)",getMykonosErrorMessage(ret), ret,pllLockStatus);
        if ((pllLockStatus & pllLock) != pllLock) {
            dev_err(&phy->spi->dev, "PLLs unlocked %x", pllLockStatus & 0x0F);
            ret = -EFAULT;
            goto out;
        }

        
        ret = MYKONOS_checkPllsLockStatus(mykDevice, &tx_pllLockStatus);
        dev_err(&phy->spi->dev, "Checking MYKONOS_checkPllsLockStatus tx_pllLockStatus value: %s (%d)",getMykonosErrorMessage(ret), ret);
        if (ret != MYKONOS_ERR_OK) {
            dev_err(&phy->spi->dev, "%s (%d)",
                getMykonosErrorMessage(ret), ret);
            ret = -EFAULT;
            goto out;
        }

        ret = MYKONOS_checkPllsLockStatus(mykDevice, &cal_pllLockStatus);
        dev_err(&phy->spi->dev, "Checking MYKONOS_checkPllsLockStatus cal_pllLockStatus value: %s (%d)",getMykonosErrorMessage(ret), ret);
        if (ret != MYKONOS_ERR_OK) {
            dev_err(&phy->spi->dev, "%s (%d)",
                getMykonosErrorMessage(ret), ret);
            ret = -EFAULT;
            goto out;
        }

    ret = ad9371_init_cal(phy, initCalMask);
        dev_err(&phy->spi->dev, "Checking this function1 %s (%d)", getMykonosErrorMessage(ret), ret);

    LOG DETAILS:

    ad9371 spi1.1: Checking MYKONOS_checkPllsLockStatus ret value: (0) and pllLockStatus value : (15)
    ad9371 spi1.1: Checking MYKONOS_checkPllsLockStatus tx_pllLockStatus value: (0)
    ad9371 spi1.1: Checking MYKONOS_checkPllsLockStatus cal_pllLockStatus value: (0)
    ad9371 spi1.1: Checking this function1 (0)


    The Reference frequency is given by AD9528 (122.88MHz) and it is stable. As on the board, there are 2 AD9371 and both AD9371 are getting reference clock frequency from one AD9528. We have not seen any issue related to image and lo leakage in first AD9371 output. But we are seeing images and LO leakage in second AD9371 output.

    Kindly suggest to me some different functions to check why there is lo leakage and image frequency.

    "Make sure you run LOL and QEC cal for best performance . "

    Can you suggest various methods for LOL and QEC cal ?

    I have already tried to enable

    • out_voltage0_lo_leakage_tracking_en
    • out_voltage0_quadrature_tracking_en
    • out_voltage1_lo_leakage_tracking_en
    • out_voltage1_quadrature_tracking_en

    It didn't help.

  • 0
    •  Analog Employees 
    on Aug 2, 2021 9:15 AM in reply to mahima90

    Is the frequency drift issue got resolved? Below shows PLL's are locked.

    pllLockStatus value : (15


    ...LO Leakage and Image are inherent to ZIF architecture. You can reduce the levels of this to within datasheet specifications by running calibrations..

    What is the difference in programming between first AD9371 and second. issue could be in the sequence on how you run the init cals on two devices. 

    If you run calibration only on second AD9371 is the calibrations working correctly. ? 

    Print LOL and QEC tracking cal status (Iteration count and update count) over time. MYKONOS_getTxQecStatus()

  • Yes, PLL's are locked. 

    As we have another four custom boards, which have 2 AD9371, and both are working. So I do not doubt the "difference in programming between first AD9371 and second". 

    "If you run calibration only on second AD9371 is the calibrations working correctly.

    - I didn't understand this part. As i know only ad9371_init_cal() function. I tried to enable

    • out_voltage0_lo_leakage_tracking_en
    • out_voltage0_quadrature_tracking_en

    But it didn't help.

    Let me check "Print LOL and QEC tracking cal status (Iteration count and update count) over time. MYKONOS_getTxQecStatus()" and I will get back to you.

  • Hi Vinod,

    AD9371 log details

    Printing MYKONOS_getTxQecStatus() status values:

    [  188.340224] ad9371 spi1.1: Checking TxQecStatus ret value : (0)
    [  188.346139] ad9371 spi1.1: ad9371_setup: error code (0)
    [  188.351360] ad9371 spi1.1: ad9371_setup: percentComplete (100)
    [  188.357189] ad9371 spi1.1: ad9371_setup: performanceMetric (0)
    [  188.363014] ad9371 spi1.1: ad9371_setup: iterCount (0)
    [  188.368145] ad9371 spi1.1: ad9371_setup: updateCount (0)