Custom AD9371 board initialization issues

TOOL:VIVADO 2018.3

Ref design :hdl_2019_r1

Dear team,

                  we have designed a custom daughter card comprise of two AD9371 transceivers and HMC7044 (clocking purpose).Now ,we tested this hardware along with ZC706.Everything is working as expected but when we test this daughter card with inhouse developed mother card which is having "XC7Z045 ffg 676 -2",one AD9371 is getting initialized successfully where as other AD9371 is facing RX initialization issue (but not TX and OBRX) as shown below

RXFramerStatus = 0x20

rx_jesd status

         Link is enabled 

         Measured Link Clock 122.879

         100100Reported Link Clock 122.880

          Lane rate 4915.200 MHz

          Lane rate/40 122.880 MHz

          Link status :Data

          SYSREF captured :yes

           SYSREF alignment error:No

rx_jesd lane 0 status :

Errors: 0

         CGS state: DATA

lanes status is 2

         Initial Frame Synchronization:N0

rx_jesd lane 1 status:

Errors:0

        CGS State :DATA

lane status is 2 

        Initial frame Synchronization :No

we are receiving ZEROS in  ADC data .From the above prints I understood that there is a issue in the AD9371 framer .Moreover framer status is 0x20 which indicates that sysref(using continuous sysref from HMC7044)  is received but the status of framer is in CGS state and in prints both link status as well as lane status are in DATA state .I am bit confused about this . As one chip is getting initialized I tried to modify the different JESD parameters of that chip to replicate the same issue which is being faced on other chip then my observations are as below 

1).when ever I am disabling the sysref to OBRX then the same RX issue is replicated and OBRX is in INIT state(I didn't understand what the relation between them).

2)When ever I introduce any delay in device clock or device sysref then I am facing different issue like link fail but not same as the above issue .

I think sysref is the major player .

Now I repeated the above experiments using ZC706 board but is working perfectly i.e if I introduce any delays also it is working moreover when I disable OBRX sysref, RX is getting initialized and OBRX is in init state only .

I was stuck at this point .Could you please guide me to resolve this issue with our custom mother board .

Thanks in advance 

B MOURYA 

           

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Parents Reply
  • Hi ,

    Thanks for the immediate response .

    I checked with the hardware design team ,there is no polarity mismatch on board 

    Ye I tried with lower data rates ,observed the same behavior.

    Could you please tell us whether the below stated statement is possible or not 

    framer status is 0x20 which indicates that sysref(using continuous sysref from HMC7044)  is received but the status of framer is in CGS state .prints are showing that both link status as well as lane status are in DATA state.

    Thanks in Advance 

    B MOURYA 

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