I'm aware that the 9371 has a stated synthesis BW of 250M but a data bandwidth of only 100M (the excess BW is used mainly for DPD purposes). I've seen ADI noting that the performance measurements assume you use the chip in this way.
But ignoring that assumption - is there any specific limitation from using higher data bandwidths for qpsk (e.g. say ~ 200Mbaud)? I expect that the digital filters and analog filters will provide excessive roll-off when using a higher data bandwidth, and I'll probably need to add some pre-emphasis to compensate for this (although won't be able to prevent it all). It seems at least plausible to me to get higher data bandwidths out of the chip if you can tolerate more degradation so I just want to confirm if my assumptions are correct.