I'am testing ADRV9371-W by vivado sdk, using the example 2018_R2/No OS. I have been bothered about 2 questions and could not find related answers in other place.
1. How to send tx1 /tx2 different baseband data? In the example file, the tx1 and tx2 send the sample baseband data,
like in the dac_core.c/dac_write_custom_data, there is a part of code：
for(index = 0; index < custom_tx_count; index++)
for (chan = 0; chan < num_tx_channels; chan++) // send the same data on all the channels
Xil_Out32(core->dac_ddr_baseaddr + index_mem * sizeof(uint32_t), custom_data_iq[index]);
It likes that the data write to the same addr twice. So if I want to send diff data to Tx1 / Tx2，what can I do?
2. for AD9371, how to implement 250M synthesis bandwidth? It is possible to use one ad9371 borad to transmit a 200M signal?
this question may have been post in the forum, but the answer is short and the ad9371 user guide could find more information. To realize a bigger transmit bandwidth like 200M,
a method that the baseband signals of TX1 and TX2 are shifted 50M to the positive and negative frequencies respectively, then the two RF signal combined to a 200M signal by a power combiner, it is OK?
firstname.lastname@example.org said:1. How to send tx1 /tx2 different baseband data? In the example file, the tx1 and tx2 send the sample baseband data,
Please post this query on https://ez.analog.com/linux-device-drivers…
Please post this query on https://ez.analog.com/linux-device-drivers/microcontroller-no-os-drivers/ forum.
email@example.com said:2. for AD9371, how to implement 250M synthesis bandwidth? It is possible to use one ad9371 borad to transmit a 200M signal?
Max bandwidth supported with AD9371 is 100 MHz and both Tx uses the same LO. The Max bandwidth supported is 100 MHz.
Tx Profile Section Tx Total RF BW and the Tx Primary Signal BW. The Tx Total RF BW in MHz is the total bandwidth used primarily by PA linerization algorithms such as digital predistortion. It is also referred to in user guides and the Wizard error messages as the “synthesis” bandwidth. It is expected that signals outside of the “Primary Signal BW” but inside the “Total RF BW” will be lower in level than the primary signals levels. As an example, a desired signal may occupy 18 MHz of bandwidth and an FPGA predistortion algorithm may linearize five times beyond that signal to reduce undesired emissions. The primary BW would then be 18 MHz and the total BW would be 90 MHz.
Thank you very much, and is it possible for ad9371 to let tx LO have different frequency offset like -10MHz, 10MHzfor tx1, tx2? is it have this funciton?
As mentioned in an earlier reply, both the Tx use the same LO.
Ok, I get it. Thank you for your reply.