I read all the topics in the forum that related to the AD9371 Sync.
the wiki shows only AD9361 (i assume that it's the same method in the AD9371). As we understand, in multiple chips the sync of the chips is related only for the data and the RF sync (phase ) will be achieved in case we will connect all chips with same LO or if we will use switching to one RX in order to sample the signal and evaluate the phase difference.
we would like to know if it's possible to say that even if the chips has difference phase, the phase difference will be the same (in this case Teta1-Teta2 will always give Delta Teta12).
In this case we can calibrate the Phase difference in the factory:
Our agenda is to calibrate all TX Outputs and RX inputs so there will be no phase difference. In order to do that we connected all AD9371 TX path to the ORX with coupler (every TX to his own ORX port). Our assumption was that the difference between the phases (even between two different chips) will be the same even if we will restart the system (we don’t care if the system is not sync as long as the difference will be the same all the time). In this case what we planned to do is to calibrate the TX phase in the factory and after that to transmit from all TX channels at the same time and then sample the signal from the ORX and calibrate the ORX path.
Then, in the field because we know what is the phase difference for every chip + Phase difference for every path it will be easy to sample the TX and correct the phase.
We would like to know if our assumption is correct. If it’s the case, we would like to have an explanation why the phase difference will be the same.
The AD9371/5 have the ability to do multi-chip synchronization (MCS), which is how it is described in the user guide. However, this does not include RF synchronization. It only includes the digital timing alignment.
Even with external LOs there can be a phase ambiguity (180/0 random offset) due to the divider applied to the input reference.
If you require this functionality it needs to be performed externally.
We Are using 4xAD9371 and we don't care about the Phase. We care about the phase difference (we want the difference between the AD9371's to be permanent).
As we design it we connected every TX output into is own ORX input (TX1 to ORX1 , TX2 to ORX2). We planned to have one time calibration for the TX path and the ORX path in the factory (to transmit all TX channels into 8 port scope and save the phase difference. after that , to see what is the phase difference between the TX output and the ORX input).
If the Phase difference between the AD9371's channels is permanent (even after restart) it will be possible to use the factory calibration as a level of reference (we measured the reference) in order to calibrate hardware phase difference changes (because of temperature and time).
If the Phase difference between the AD9371's is not the same every time ( let's say that between TX1 and TX4 one time the Delta = 30 deg and after reboot it will be Delta=40 deg) we will not be able to use this method.
Please advise what can we do because currently now we are not using External LO and we don't have switches matrix.
we are only using ORX feedbacks + calibration in the factory for Delta Phases.
The phase difference between AD9371's can be random from every power-up or reset. You have to do one-time phase calibration for every power-up or reset.
OK, Please explain why?
As far as i understand the AD9528 Block diagram , the Phase deference between the 122.88MHz Clocks that goes into each AD9371 chip is Permanent. If the AD9371 PLL using the Clock it will be locked all the time on the same phase deference.. As far as i understand the Pase will change randomly but to all of the together and it's why i don't understand how is it possible to say that the Phase deference will change also randomly.
Please explain you answer.
AD9371 provides only baseband synchronization( you can use the MCS functionality to time-align all the digital clocks)and not RF synchronisation.
With every boot up the way the signal reaches will be different and hence the phase will be different. For RFPLL phase sync if you are referencing the phase of each LO w.r.t the REF_CLk then with each boot up, the phase of the LO w.r.t the REF_CLK will change and hence the phase difference also changes with every boot up.