I would like some advice on how to understand and fix the root cause of error flags tripping in the transmit path. I am using the AD9371 evaluation board, with a Xilinx ZCU102 FPGA eval board.
The transmit path is being fed a digitally generated sine wave for "I" and the 90 degree offset "Q" signal over JESD. I have a simple control over amplitude by shifting (ie/ dividing by 2). So generate a full range signal, then half range, quarter range etc. Giving 8 output levels (call them 0dB to -42dB in -6dB steps). I can understand a full range signal allows no headroom for the calibration routines supported by the ARM device inside the transceiver, as they alter the gain of the paths - and in this case a spectrum analyser on the output series of harmonics at the test tone frequency. These disappear with a slight reduction of input signal.
However, I am finding the error flags trip (and latch) when switching on much lower signals between -6dB to -18dB. So at the moment I am restricting measurements to -24dB and below. This loses a lot of dynamic range (1/16th of full range).
The HB1, HB2 and QEC flags trip. The 4th PFIR flag never seems to trip.
There seems to be little available information to debug the transmit path signals, just the latching error flags.
Any ideas to investigate/fix?