I would like some advice on how to understand and fix the root cause of error flags tripping in the transmit path. I am using the AD9371 evaluation board, with a Xilinx ZCU102 FPGA eval board.
The transmit path is being fed a digitally generated sine wave for "I" and the 90 degree offset "Q" signal over JESD. I have a simple control over amplitude by shifting (ie/ dividing by 2). So generate a full range signal, then half range, quarter range etc. Giving 8 output levels (call them 0dB to -42dB in -6dB steps). I can understand a full range signal allows no headroom for the calibration routines supported by the ARM device inside the transceiver, as they alter the gain of the paths - and in this case a spectrum analyser on the output series of harmonics at the test tone frequency. These disappear with a slight reduction of input signal.
However, I am finding the error flags trip (and latch) when switching on much lower signals between -6dB to -18dB. So at the moment I am restricting measurements to -24dB and below. This loses a lot of dynamic range (1/16th of full range).
The HB1, HB2 and QEC flags trip. The 4th PFIR flag never seems to trip.
There seems to be little available information to debug the transmit path signals, just the latching error flags.
Any ideas to investigate/fix?
How are you checking that the error flag is tripping? How are you feeding the data to the transmitter input?
Are you using the DAC BUFFER OUTPUT option in IIO GUI to feed the data?
I am using the Mykonos headless SW to build embedded test SW. I am using the AD9371 evaluation board, so to access the transmit chain flags I first run the initialisation method as provided by ADI, then call setupGpioMonitor() which I added to setup the GPIO to monitor the transmit error flags (attached snippet of code in file below). I then monitor signals with DSO on the header provided on the eval board (P502).
I have my own FPGA design using a Xilinx zcu102 board. This provides the JESD204 interfaces. The transmit input currently is a DDS which produces a sinewave, and a 90 degree offset sinewave for I and Q.
I am not sure what the IIO GUI you refer to is. But I am not using any ADI GUI. I have a serial link to the ARM running inside the FPGA which hosts the embedded SW. This provides a simple command line GUI. I assume the DAC BUFFER OUTPUT option is a mode specific to your GUI - please confirm.
You can refer our no -OS implementation and HDL reference design
AD9371/AD9375 No-OS Setup [Analog Devices Wiki]
ADRV9371 HDL Reference Design [Analog Devices Wiki]
What is data format of IQ signal feed to chip? it should be 2's complement.
Thanks for the wiki links. I searched both for "DAC BUFFER OUTPUT" and found 1 reference in https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt?s=dac&s=buffer&s=output .
This seems to indicate its a "Transmit/DDS mode " for the specific FPGA design used.
The format of the IQ data is 2's complement. The DDS operation has been checked with both simulation, and internal ILA.
Is there any debug help / instrumentation on the transmit path other than these latching error flags?
Can the error flags be changed to non-latching?
We tried with the same setting as yours but could not reproduce the issue. All the error flags(HB1 ns TXFIR) are properly tripping with a decrease in input signal scaling(from 0dbfs to -3dbfs).
There might be some problem with the IQ data that you are using.