AD9371 ADC I/Q imbalance

I am using AD9371 in my custom board and there is a problam.

When using AD9371 to receive a 1Mhz baseband single tone signal, the amplitude of in-phase and quadrature are sometimes imbalance.

I tried to readback the status of QEC and it is always pending.

So why is this problem and is this related to the RF frequency?

IQrate is 64MHz and LO is1GHz. Thanks!

    •  Analog Employees 
    on Apr 9, 2020 9:51 AM

    What is the time interval after which you are seeing this amp imbalance? Are you running RXQEC tracking cal?

  • I use the zynq PS to configure the AD9371. After the configuration is completed, 90% of the cases may occur. If this happens, it will always exist during this power-on.
    I ran the tracking calibration, but the situation still exists when the tracking calibration is turned off.
    What I don't understand is that I use the same code to configure two AD9371s at the same time. This situation always appears on the RX1 channel of the second slice (rx3 in the above picture).
    Do you have any good suggestions? Thank you!
    The following is my configuration(where RF0 represents the first piece 9371, RF1 represents the second piece 9371):

    **************************************************

    ****system initialization sequence is begining****

    **************************************************

    Please wait...

    start config lmk04828 

    lmk04828 pll1 locked!

    lmk04828 pll2 locked!

    RF0,MCS successful

    RF0,CLKPLL locked

    RF0,AD9371 ARM version 5.1.1

    RF0,PLLs locked

    RF0,Calibrations completed successfully

    lane_rate_khz= 1280000 use cpll:refclk_div= 16,out_div= 2,fbdiv_45= 1,fbdiv= 2

    lane_rate_khz= 2560000 use cpll:refclk_div= 16,out_div= 1,fbdiv_45= 1,fbdiv= 2

    lane_rate_khz= 2560000 use cpll:refclk_div= 16,out_div= 1,fbdiv_45= 1,fbdiv= 2

    default txpll sel=0

    tx_jesd_rf is locking!

    rx_jesd_rf is locking!

    orx_jesd_rf is locking!

    RF1,MCS successful

    RF1,CLKPLL locked

    RF1,AD9371 ARM version 5.1.1

    RF1,PLLs locked

    RF1,Calibrations completed successfully

    lane_rate_khz= 1280000 use cpll:refclk_div= 16,out_div= 2,fbdiv_45= 1,fbdiv= 2

    lane_rate_khz= 2560000 use cpll:refclk_div= 16,out_div= 1,fbdiv_45= 1,fbdiv= 2

    lane_rate_khz= 2560000 use cpll:refclk_div= 16,out_div= 1,fbdiv_45= 1,fbdiv= 2

    default txpll sel=0

    tx_jesd_rf is locking!

    rx_jesd_rf is locking!

    orx_jesd_rf is locking!

    ***************************************************

    *******current configuration times is 1 !*******

    *********system initialization complete !********

    *****************************************************

    •  Analog Employees 
    on Apr 13, 2020 2:39 PM in reply to shck

    The RF matching is critical for QEC calibration to succeed. You can try matching your board for the frequency of interest and try terminating the port while running cals.

    If you skip QEC cal is the software running without error. Are you seeing large offset in this case,?

    On The second device device , the second Rx channel is working fine and issue is only with Rx1 ? In that case you can check if Balun is mounted properly and there are no physical damage. 

    Are you seeing same behavior across multiple boards?