Setting AD9371 for 80MHz sampling clk

Hello All,

I’m using AD9371 for advanced Wi-Fi prototyping. Hence I had to change 122.88MHz VCXO on evaluation board to 80MHz so I can achieve integer multiples of 20MHz sampling required for 802.11 signal processing.

By  doing so, I discover a number of issues, particularly with initial calibration routine in AD9371 firmware and driver. Below are details of my discovery and workaround I find to make it work. Could you please review it and subject the better way to make AD9371 work for 80MHz sampling clk, Thanks, Mikhail.

Here are details:

1.By enabling  ad9371 evaluation board to run at 80MHz clk I discover a multiple issues with Filter Designer for AD9371, AD9371 calibration firmware routine and a driver. While I found a workaround, we asking to address this issue as it preventing us to use AD9371 in normal operation mode.

2.Attached are word document and supporting files (.m file, profile & .dts) with necessary information to make ad9371 work 80MHz clk so I&Q sampling rate is integer multiplier of 20MHz (as it used for 802.11/WI-FI).

ad9371_80MHz_profileMTG.txt
<profile AD9371 version=0 name=Rx 40, IQrate 80.000>
 <clocks>
  <deviceClock_kHz=320000>
  <clkPllVcoFreq_kHz=9600000>
  <clkPllVcoDiv=3>
  <clkPllHsDiv=4>
 </clocks>

 <rx>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=1>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=40000>

  <filter FIR gain=-6 num=48>
  1
  7
  3
  -20
  -38
  10
  107
  100
  -122
  -334
  -113
  506
  718
  -166
  -1391
  -1095
  1231
  3033
  981
  -4224
  -6482
  219
  14325
  26107
  26107
  14325
  219
  -6482
  -4224
  981
  3033
  1231
  -1095
  -1391
  -166
  718
  506
  -113
  -334
  -122
  100
  107
  10
  -38
  -20
  3
  7
  1
  </filter>

  <adc-profile num=16>
  900
  559
  201
  98
  1280
  199
  1522
  98
  860
  25
  529
  37
  48
  26
  15
  196
  </adc-profile>
 </rx>

 <obs>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=1>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=48>
  -1
  10
  10
  -22
  -60
  -6
  143
  171
  -129
  -485
  -245
  660
  1099
  -74
  -1954
  -1784
  1506
  4443
  1920
  -5737
  -10210
  -2631
  15550
  31189
  31189
  15550
  -2631
  -10210
  -5737
  1920
  4443
  1506
  -1784
  -1954
  -74
  1099
  660
  -245
  -485
  -129
  171
  143
  -6
  -60
  -22
  10
  10
  -1
  </filter>

  <adc-profile num=16>
  900
  559
  201
  98
  1280
  199
  1522
  98
  860
  25
  529
  37
  48
  26
  15
  196
  </adc-profile>

  <lpbk-adc-profile num=16>
  922
  550
  201
  98
  1280
  112
  1505
  53
  864
  14
  533
  40
  48
  26
  15
  197
  </lpbk-adc-profile>
 </obs>

 <sniffer>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=40000>
  <rfBandwidth_Hz=20000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -9
  12
  18
  17
  -17
  -49
  -45
  21
  99
  105
  -11
  -171
  -215
  -36
  258
  390
  149
  -343
  -648
  -371
  394
  1003
  763
  -357
  -1476
  -1425
  138
  2113
  2589
  489
  -3082
  -5079
  -2537
  4990
  14500
  21095
  21095
  14500
  4990
  -2537
  -5079
  -3082
  489
  2589
  2113
  138
  -1425
  -1476
  -357
  763
  1003
  394
  -371
  -648
  -343
  149
  390
  258
  -36
  -215
  -171
  -11
  105
  99
  21
  -45
  -49
  -17
  17
  18
  12
  -9
  </filter>

  <adc-profile num=16>
  922
  550
  201
  98
  1280
  112
  1505
  53
  864
  14
  533
  40
  48
  26
  15
  197
  </adc-profile>
 </sniffer>

 <tx>
  <dacDiv=2.5>
  <txFirInterpolation=1>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <txInputHbInterpolation=1>
  <iqRate_kHz=80000>
  <primarySigBandwidth_Hz=20000000>
  <rfBandwidth_Hz=40000000>
  <txDac3dBCorner_kHz=92000>
  <txBbf3dBCorner_kHz=20000>

  <filter FIR gain=6 num=16>
  26
  -292
  -75
  333
  339
  -659
  -2192
  21034
  -2192
  -659
  339
  333
  -75
  -292
  26
  0
  </filter>
 </tx>
</profile>

DOCX

3.The main issue addressed by outlined work around:

3.1. Even with correct modification to Linux Device Tree, initial initialization of AD9371 at boot up is failing due to a time out of driver waiting for calibration routine execution in AD9371 firmware.

[    3.560034] random: crng init done

[   84.532030] ERROR: 283: MYKONOS_waitInitCals() returned an ARM error

[   84.557234] ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()

[   84.591936] ERROR: 364: MYKONOS_waitArmCmdStatus() exited due to ARM error for the desired ARM opcode

[   84.601111] ERROR: 145: ARM command to move to radioOn state failed.

[   84.608698] ERROR: 364: MYKONOS_waitArmCmdStatus() exited due to ARM error for the desired ARM opcode

[   84.617880] ERROR: 257: ARM Command Error in MYKONOS_setObsRxPathSource()

3.2. It was discovered that if TX_QEC_INIT calibration flag is disabled, Driver is not failing anymore. TX is operate fine after that but RX still not working. 

% Dis TX_QEC_INIT Calibration using command line

cd /sys/kernel/debug/iio/iio:device1

echo 31231 > /sys/kernel/debug/iio/iio:device1/adi,default-initial-calibrations-mask

echo 1 > /sys/kernel/debug/iio/iio:device1/initialize

3.3. It was discovered that the profile, exactly the same as AD9371 configuration in Linux Device Tree has to be reload as the net step to make RX chain working (the MATLAB script is used).

h = intelsoc;

ProfileFile = 'ad9371_80MHz_profileMTG.txt';

h.putFile(ProfileFile,'/tmp') % FTP the configuration file over

ProfileConfigLocation = h.system('ls /sys/bus/iio/devices/iio:device*/*profile_config*');

ProfileConfigWrite = sprintf('cat /tmp/%s > %s',ProfileFile,ProfileConfigLocation);

msg = h.system(ProfileConfigWrite);

  • Here is .m file I sed to automate a setup (disabling TX_QEC_INIT Calibration & loading profile)

    •  Analog Employees 
    on Jan 9, 2019 8:16 AM in reply to mgaleev

    The first problem that needs to get addressed is the profile generation issue.

    Modifying or fixing a profile by hand is a bad idea, there might be some constrains that are not met and thus the profile is generated the way it is.

    Of course in case it's obviously buggy, fixing it does not mean it must work the way it's being modified.

    The next issue is the failing TX QEC INIT calibration, which can be a result of an invalid profile.

    Have you tried using a device clock of 80 MHz ?

    Can you attach your modified devicetree dts?

    I'll move this thread to the AD9371 design support forum for further inputs on the filter designer issue.

    -Michael

     

  • For some reasons I cant’t copy a file to the post, so here is a text copy of .dts file:

    /dts-v1/;

     

    / {

                   #address-cells = <0x1>;

                   #size-cells = <0x1>;

                   model = "Altera SOCFPGA Arria 10";

                   compatible = "altr,socfpga-arria10", "altr,socfpga";

     

                   chosen {

                                  bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p3 rw rootwait earlyprintk";

                                  stdout-path = "serial0:115200n8";

                   };

     

                   aliases {

                                  ethernet0 = "/soc/ethernet@ff800000";

                                  serial0 = "/soc/serial1@ffc02100";

                   };

     

                   memory {

                                  device_type = "memory";

                                  reg = <0x0 0x40000000>;

                   };

     

                   cpus {

                                  #address-cells = <0x1>;

                                  #size-cells = <0x0>;

                                  enable-method = "altr,socfpga-a10-smp";

     

                                  cpu@0 {

                                                 compatible = "arm,cortex-a9";

                                                 device_type = "cpu";

                                                 reg = <0x0>;

                                                 next-level-cache = <0x1>;

                                  };

     

                                  cpu@1 {

                                                 compatible = "arm,cortex-a9";

                                                 device_type = "cpu";

                                                 reg = <0x1>;

                                                 next-level-cache = <0x1>;

                                  };

                   };

     

                   intc@ffffd000 {

                                  compatible = "arm,cortex-a9-gic";

                                  #interrupt-cells = <0x3>;

                                  interrupt-controller;

                                  reg = <0xffffd000 0x1000 0xffffc100 0x100>;

                                  linux,phandle = <0x2>;

                                  phandle = <0x2>;

                   };

     

                   soc {

                                  #address-cells = <0x1>;

                                  #size-cells = <0x1>;

                                  compatible = "simple-bus";

                                  device_type = "soc";

                                  interrupt-parent = <0x2>;

                                  ranges;

     

                                  amba {

                                                 compatible = "simple-bus";

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x1>;

                                                 ranges;

     

                                                 pdma@ffda1000 {

                                                                compatible = "arm,pl330", "arm,primecell";

                                                                reg = <0xffda1000 0x1000>;

                                                                interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4 0x0 0x56 0x4 0x0 0x57 0x4 0x0 0x58 0x4 0x0 0x59 0x4 0x0 0x5a 0x4 0x0 0x5b 0x4>;

                                                                #dma-cells = <0x1>;

                                                                #dma-channels = <0x8>;

                                                                #dma-requests = <0x20>;

                                                                clocks = <0x3>;

                                                                clock-names = "apb_pclk";

                                                                microcode-cached;

                                                                linux,phandle = <0x1b>;

                                                                phandle = <0x1b>;

                                                 };

                                  };

     

                                  base_fpga_region {

                                                 #address-cells = <0x2>;

                                                 #size-cells = <0x1>;

                                                 compatible = "fpga-region", "simple-bus";

                                                 fpga-mgr = <0x4>;

                                                 ranges = <0x0 0x0 0xc0000000 0x20000000 0x1 0x0 0xff200000 0x200000>;

     

                                                 bridge0@0x0 {

                                                                compatible = "simple-bus";

                                                                #size-cells = <0x1>;

                                                                #address-cells = <0x1>;

                                                                ranges = <0x0 0x0 0x0 0x20000000>;

     

                                                                mwipcore@0x00000000 {

                                                                               compatible = "mathworks,mwipcore-v3.00";

                                                                               reg = <0x0 0x10000>;

                                                                               #address-cells = <0x1>;

                                                                               #size-cells = <0x0>;

     

                                                                               mmrd-channel@0 {

                                                                                              reg = <0x0>;

                                                                                              compatible = "mathworks,mm-read-channel-v1.00";

                                                                                              mathworks,dev-name = "mmrd0";

                                                                               };

     

                                                                               mmwr-channel@1 {

                                                                                              reg = <0x1>;

                                                                                              compatible = "mathworks,mm-write-channel-v1.00";

                                                                                              mathworks,dev-name = "mmwr0";

                                                                               };

                                                                };

                                                 };

     

                                                 bridge1@0x1 {

                                                                compatible = "simple-bus";

                                                                #size-cells = <0x1>;

                                                                #address-cells = <0x1>;

                                                                ranges = <0x0 0x1 0x0 0x200000>;

                                                 };

                                  };

     

                                  clkmgr@ffd04000 {

                                                 compatible = "altr,clk-mgr";

                                                 reg = <0xffd04000 0x1000>;

     

                                                 clocks {

                                                                #address-cells = <0x1>;

                                                                #size-cells = <0x0>;

     

                                                                cb_intosc_hs_div2_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "fixed-clock";

                                                                               linux,phandle = <0xd>;

                                                                               phandle = <0xd>;

                                                                };

     

                                                                cb_intosc_ls_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "fixed-clock";

                                                                               linux,phandle = <0x6>;

                                                                               phandle = <0x6>;

                                                                };

     

                                                                f2s_free_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "fixed-clock";

                                                                               linux,phandle = <0x7>;

                                                                               phandle = <0x7>;

                                                                };

     

                                                                osc1 {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "fixed-clock";

                                                                               clock-frequency = <0x17d7840>;

                                                                               linux,phandle = <0x5>;

                                                                               phandle = <0x5>;

                                                                };

     

                                                                main_pll {

                                                                               #address-cells = <0x1>;

                                                                               #size-cells = <0x0>;

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-pll-clock";

                                                                               clocks = <0x5 0x6 0x7>;

                                                                               reg = <0x40>;

                                                                               linux,phandle = <0x8>;

                                                                               phandle = <0x8>;

     

                                                                               main_mpu_base_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              div-reg = <0x140 0x0 0xb>;

                                                                                              linux,phandle = <0xb>;

                                                                                              phandle = <0xb>;

                                                                               };

     

                                                                               main_noc_base_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              div-reg = <0x144 0x0 0xb>;

                                                                                              linux,phandle = <0xe>;

                                                                                              phandle = <0xe>;

                                                                               };

     

                                                                               main_emaca_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x68>;

                                                                               };

     

                                                                               main_emacb_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x6c>;

                                                                               };

     

                                                                               main_emac_ptp_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x70>;

                                                                               };

     

                                                                               main_gpio_db_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x74>;

                                                                               };

     

                                                                               main_sdmmc_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x78>;

                                                                                              linux,phandle = <0x12>;

                                                                                              phandle = <0x12>;

                                                                               };

     

                                                                               main_s2f_usr0_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x7c>;

                                                                               };

     

                                                                               main_s2f_usr1_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x80>;

                                                                                              linux,phandle = <0x10>;

                                                                                              phandle = <0x10>;

                                                                               };

     

                                                                               main_hmc_pll_ref_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x84>;

                                                                               };

     

                                                                               main_periph_ref_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0x8>;

                                                                                              reg = <0x9c>;

                                                                                              linux,phandle = <0x9>;

                                                                                              phandle = <0x9>;

                                                                               };

                                                                };

     

                                                                periph_pll {

                                                                               #address-cells = <0x1>;

                                                                               #size-cells = <0x0>;

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-pll-clock";

                                                                               clocks = <0x5 0x6 0x7 0x9>;

                                                                               reg = <0xc0>;

                                                                               linux,phandle = <0xa>;

                                                                               phandle = <0xa>;

     

                                                                               peri_mpu_base_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              div-reg = <0x140 0x10 0xb>;

                                                                                              linux,phandle = <0xc>;

                                                                                              phandle = <0xc>;

                                                                               };

     

                                                                               peri_noc_base_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              div-reg = <0x144 0x10 0xb>;

                                                                                              linux,phandle = <0xf>;

                                                                                              phandle = <0xf>;

                                                                               };

     

                                                                               peri_emaca_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0xe8>;

                                                                               };

     

                                                                               peri_emacb_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0xec>;

                                                                               };

     

                                                                               peri_emac_ptp_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0xf0>;

                                                                               };

     

                                                                               peri_gpio_db_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0xf4>;

                                                                               };

     

                                                                               peri_sdmmc_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0xf8>;

                                                                                              linux,phandle = <0x13>;

                                                                                              phandle = <0x13>;

                                                                               };

     

                                                                               peri_s2f_usr0_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0xfc>;

                                                                               };

     

                                                                               peri_s2f_usr1_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0x100>;

                                                                                              linux,phandle = <0x11>;

                                                                                              phandle = <0x11>;

                                                                               };

     

                                                                               peri_hmc_pll_ref_clk {

                                                                                              #clock-cells = <0x0>;

                                                                                              compatible = "altr,socfpga-a10-perip-clk";

                                                                                              clocks = <0xa>;

                                                                                              reg = <0x104>;

                                                                               };

                                                                };

     

                                                                mpu_free_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-perip-clk";

                                                                               clocks = <0xb 0xc 0x5 0xd 0x7>;

                                                                               reg = <0x60>;

                                                                               linux,phandle = <0x15>;

                                                                               phandle = <0x15>;

                                                                };

     

                                                                noc_free_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-perip-clk";

                                                                               clocks = <0xe 0xf 0x5 0xd 0x7>;

                                                                               reg = <0x64>;

                                                                               linux,phandle = <0x14>;

                                                                               phandle = <0x14>;

                                                                };

     

                                                                s2f_user1_free_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-perip-clk";

                                                                               clocks = <0x10 0x11 0x5 0xd 0x7>;

                                                                               reg = <0x104>;

                                                                };

     

                                                                sdmmc_free_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-perip-clk";

                                                                               clocks = <0x12 0x13 0x5 0xd 0x7>;

                                                                               fixed-divider = <0x4>;

                                                                               reg = <0xf8>;

                                                                               linux,phandle = <0x16>;

                                                                               phandle = <0x16>;

                                                                };

     

                                                                l4_sys_free_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-perip-clk";

                                                                               clocks = <0x14>;

                                                                               fixed-divider = <0x4>;

                                                                               linux,phandle = <0x25>;

                                                                               phandle = <0x25>;

                                                                };

     

                                                                l4_main_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x14>;

                                                                               div-reg = <0xa8 0x0 0x2>;

                                                                               clk-gate = <0x48 0x1>;

                                                                               linux,phandle = <0x3>;

                                                                               phandle = <0x3>;

                                                                };

     

                                                                l4_mp_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x14>;

                                                                               div-reg = <0xa8 0x8 0x2>;

                                                                               clk-gate = <0x48 0x2>;

                                                                               linux,phandle = <0x17>;

                                                                               phandle = <0x17>;

                                                                };

     

                                                                l4_sp_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x14>;

                                                                               div-reg = <0xa8 0x10 0x2>;

                                                                               clk-gate = <0x48 0x3>;

                                                                               linux,phandle = <0x1a>;

                                                                               phandle = <0x1a>;

                                                                };

     

                                                                mpu_periph_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x15>;

                                                                               fixed-divider = <0x4>;

                                                                               clk-gate = <0x48 0x0>;

                                                                               linux,phandle = <0x24>;

                                                                               phandle = <0x24>;

                                                                };

     

                                                                sdmmc_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x16>;

                                                                               clk-gate = <0xc8 0x5>;

                                                                               clk-phase = <0x0 0x87>;

                                                                               linux,phandle = <0x1e>;

                                                                               phandle = <0x1e>;

                                                                };

     

                                                                qspi_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x3>;

                                                                               clk-gate = <0xc8 0xb>;

                                                                               linux,phandle = <0x23>;

                                                                               phandle = <0x23>;

                                                                };

     

                                                                nand_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x17>;

                                                                               clk-gate = <0xc8 0xa>;

                                                                               linux,phandle = <0x1f>;

                                                                               phandle = <0x1f>;

                                                                };

     

                                                                spi_m_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x3>;

                                                                               clk-gate = <0xc8 0x9>;

                                                                               linux,phandle = <0x1c>;

                                                                               phandle = <0x1c>;

                                                                };

     

                                                                usb_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x17>;

                                                                               clk-gate = <0xc8 0x8>;

                                                                               linux,phandle = <0x26>;

                                                                               phandle = <0x26>;

                                                                };

     

                                                                s2f_usr1_clk {

                                                                               #clock-cells = <0x0>;

                                                                               compatible = "altr,socfpga-a10-gate-clk";

                                                                               clocks = <0x11>;

                                                                               clk-gate = <0xc8 0x6>;

                                                                };

                                                 };

                                  };

     

                                  ethernet@ff800000 {

                                                 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

                                                 altr,sysmgr-syscon = <0x18 0x44 0x0>;

                                                 reg = <0xff800000 0x2000>;

                                                 interrupts = <0x0 0x5c 0x4>;

                                                 interrupt-names = "macirq";

                                                 mac-address = [00 00 00 00 00 00];

                                                 snps,multicast-filter-bins = <0x100>;

                                                 snps,perfect-filter-entries = <0x80>;

                                                 tx-fifo-depth = <0x1000>;

                                                 rx-fifo-depth = <0x4000>;

                                                 clocks = <0x17>;

                                                 clock-names = "stmmaceth";

                                                 resets = <0x19 0x20>;

                                                 reset-names = "stmmaceth";

                                                 status = "okay";

                                                 phy-mode = "rgmii";

                                                 phy-addr = <0xffffffff>;

                                                 txd0-skew-ps = <0x0>;

                                                 txd1-skew-ps = <0x0>;

                                                 txd2-skew-ps = <0x0>;

                                                 txd3-skew-ps = <0x0>;

                                                 rxd0-skew-ps = <0x1a4>;

                                                 rxd1-skew-ps = <0x1a4>;

                                                 rxd2-skew-ps = <0x1a4>;

                                                 rxd3-skew-ps = <0x1a4>;

                                                 txen-skew-ps = <0x0>;

                                                 txc-skew-ps = <0x744>;

                                                 rxdv-skew-ps = <0x1a4>;

                                                 rxc-skew-ps = <0x690>;

                                                 max-frame-size = <0xed8>;

                                                 linux,phandle = <0x21>;

                                                 phandle = <0x21>;

                                  };

     

                                  ethernet@ff802000 {

                                                 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

                                                 altr,sysmgr-syscon = <0x18 0x48 0x0>;

                                                 reg = <0xff802000 0x2000>;

                                                 interrupts = <0x0 0x5d 0x4>;

                                                 interrupt-names = "macirq";

                                                 mac-address = [00 00 00 00 00 00];

                                                 snps,multicast-filter-bins = <0x100>;

                                                 snps,perfect-filter-entries = <0x80>;

                                                 tx-fifo-depth = <0x1000>;

                                                 rx-fifo-depth = <0x4000>;

                                                 clocks = <0x17>;

                                                 clock-names = "stmmaceth";

                                                 resets = <0x19 0x21>;

                                                 reset-names = "stmmaceth";

                                                 status = "disabled";

                                  };

     

                                  ethernet@ff804000 {

                                                 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

                                                 altr,sysmgr-syscon = <0x18 0x4c 0x0>;

                                                 reg = <0xff804000 0x2000>;

                                                 interrupts = <0x0 0x5e 0x4>;

                                                 interrupt-names = "macirq";

                                                 mac-address = [00 00 00 00 00 00];

                                                 snps,multicast-filter-bins = <0x100>;

                                                 snps,perfect-filter-entries = <0x80>;

                                                 tx-fifo-depth = <0x1000>;

                                                 rx-fifo-depth = <0x4000>;

                                                 clocks = <0x17>;

                                                 clock-names = "stmmaceth";

                                                 status = "disabled";

                                  };

     

                                  gpio@ffc02900 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,dw-apb-gpio";

                                                 reg = <0xffc02900 0x100>;

                                                 status = "disabled";

     

                                                 gpio-controller@0 {

                                                                compatible = "snps,dw-apb-gpio-port";

                                                                gpio-controller;

                                                                #gpio-cells = <0x2>;

                                                                snps,nr-gpios = <0x1d>;

                                                                reg = <0x0>;

                                                                interrupt-controller;

                                                                #interrupt-cells = <0x2>;

                                                                interrupts = <0x0 0x70 0x4>;

                                                 };

                                  };

     

                                  gpio@ffc02a00 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,dw-apb-gpio";

                                                 reg = <0xffc02a00 0x100>;

                                                 status = "okay";

     

                                                 gpio-controller@0 {

                                                                compatible = "snps,dw-apb-gpio-port";

                                                                gpio-controller;

                                                                #gpio-cells = <0x2>;

                                                                snps,nr-gpios = <0x1d>;

                                                                reg = <0x0>;

                                                                interrupt-controller;

                                                                #interrupt-cells = <0x2>;

                                                                interrupts = <0x0 0x71 0x4>;

                                                                linux,phandle = <0x1d>;

                                                                phandle = <0x1d>;

                                                 };

                                  };

     

                                  gpio@ffc02b00 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,dw-apb-gpio";

                                                 reg = <0xffc02b00 0x100>;

                                                 status = "disabled";

     

                                                 gpio-controller@0 {

                                                                compatible = "snps,dw-apb-gpio-port";

                                                                gpio-controller;

                                                                #gpio-cells = <0x2>;

                                                                snps,nr-gpios = <0x1b>;

                                                                reg = <0x0>;

                                                                interrupt-controller;

                                                                #interrupt-cells = <0x2>;

                                                                interrupts = <0x0 0x72 0x4>;

                                                 };

                                  };

     

                                  fpga-mgr@ffd03000 {

                                                 compatible = "altr,socfpga-a10-fpga-mgr";

                                                 reg = <0xffd03000 0x100 0xffcfe400 0x20>;

                                                 clocks = <0x17>;

                                                 resets = <0x19 0x83>;

                                                 reset-names = "fpgamgr";

                                                 linux,phandle = <0x4>;

                                                 phandle = <0x4>;

                                  };

     

                                  i2c@ffc02200 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,designware-i2c";

                                                 reg = <0xffc02200 0x100>;

                                                 interrupts = <0x0 0x69 0x4>;

                                                 clocks = <0x1a>;

                                                 status = "disabled";

                                  };

     

                                  i2c@ffc02300 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,designware-i2c";

                                                 reg = <0xffc02300 0x100>;

                                                 interrupts = <0x0 0x6a 0x4>;

                                                 clocks = <0x1a>;

                                                 status = "okay";

                                                 clock-frequency = <0x186a0>;

                                                 i2c-sda-falling-time-ns = <0x1770>;

                                                 i2c-scl-falling-time-ns = <0x1770>;

     

                                                 lcd@28 {

                                                                compatible = "newhaven,nhd-0216k3z-nsw-bbw";

                                                                reg = <0x28>;

                                                                height = <0x2>;

                                                                width = <0x10>;

                                                                brightness = <0x8>;

                                                 };

     

                                                 eeprom@51 {

                                                                compatible = "atmel,24c32";

                                                                reg = <0x51>;

                                                                pagesize = <0x20>;

                                                 };

     

                                                 rtc@68 {

                                                                compatible = "dallas,ds1339";

                                                                reg = <0x68>;

                                                 };

     

                                                 max@4c {

                                                                compatible = "max1619";

                                                                reg = <0x4c>;

                                                 };

     

                                                 ltc@5c {

                                                                compatible = "ltc2977";

                                                                reg = <0x5c>;

                                                 };

                                  };

     

                                  i2c@ffc02400 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,designware-i2c";

                                                 reg = <0xffc02400 0x100>;

                                                 interrupts = <0x0 0x6b 0x4>;

                                                 clocks = <0x1a>;

                                                 status = "disabled";

                                  };

     

                                  i2c@ffc02500 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,designware-i2c";

                                                 reg = <0xffc02500 0x100>;

                                                 interrupts = <0x0 0x6c 0x4>;

                                                 clocks = <0x1a>;

                                                 status = "disabled";

                                  };

     

                                  i2c@ffc02600 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "snps,designware-i2c";

                                                 reg = <0xffc02600 0x100>;

                                                 interrupts = <0x0 0x6d 0x4>;

                                                 clocks = <0x1a>;

                                                 status = "disabled";

                                  };

     

                                  spi@ffda5000 {

                                                 compatible = "snps,dw-apb-ssi";

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 reg = <0xffda5000 0x100>;

                                                 interrupts = <0x0 0x66 0x4>;

                                                 num-chipselect = <0x4>;

                                                 bus-num = <0x0>;

                                                 tx-dma-channel = <0x1b 0x10>;

                                                 rx-dma-channel = <0x1b 0x11>;

                                                 clocks = <0x1c>;

                                                 status = "okay";

     

                                                 resource-manager@0 {

                                                                compatible = "altr,a10sr";

                                                                reg = <0x0>;

                                                                spi-max-frequency = <0x186a0>;

                                                                interrupt-parent = <0x1d>;

                                                                interrupts = <0x5 0x8>;

                                                                interrupt-controller;

                                                                #interrupt-cells = <0x2>;

     

                                                                gpio-controller {

                                                                               compatible = "altr,a10sr-gpio";

                                                                               gpio-controller;

                                                                               #gpio-cells = <0x2>;

                                                                               linux,phandle = <0x39>;

                                                                               phandle = <0x39>;

                                                                };

     

                                                                ps_alarm {

                                                                               compatible = "altr,a10sr-hwmon";

                                                                };

                                                 };

                                  };

     

                                  sdr@ffc25000 {

                                                 compatible = "altr,sdr-ctl", "syscon";

                                                 reg = <0xffcfb100 0x80>;

                                                 linux,phandle = <0x20>;

                                                 phandle = <0x20>;

                                  };

     

                                  l2-cache@fffff000 {

                                                 compatible = "arm,pl310-cache";

                                                 reg = <0xfffff000 0x1000>;

                                                 interrupts = <0x0 0x12 0x4>;

                                                 cache-unified;

                                                 cache-level = <0x2>;

                                                 prefetch-data = <0x1>;

                                                 prefetch-instr = <0x1>;

                                                 arm,shared-override;

                                                 linux,phandle = <0x1>;

                                                 phandle = <0x1>;

                                  };

     

                                  dwmmc0@ff808000 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 compatible = "altr,socfpga-dw-mshc";

                                                 reg = <0xff808000 0x1000>;

                                                 interrupts = <0x0 0x62 0x4>;

                                                 fifo-depth = <0x400>;

                                                 clocks = <0x17 0x1e>;

                                                 clock-names = "biu", "ciu";

                                                 status = "okay";

                                                 num-slots = <0x1>;

                                                 cap-sd-highspeed;

                                                 broken-cd;

                                                 bus-width = <0x4>;

                                                 altr,dw-mshc-ciu-div = <0x3>;

                                                 altr,dw-mshc-sdr-timing = <0x0 0x3>;

                                  };

     

                                  nand@ffb90000 {

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x1>;

                                                 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";

                                                 reg = <0xffb90000 0x72000 0xffb80000 0x10000>;

                                                 reg-names = "nand_data", "denali_reg";

                                                 interrupts = <0x0 0x63 0x4>;

                                                 dma-mask = <0xffffffff>;

                                                 clocks = <0x1f>;

                                                 status = "disabled";

                                  };

     

                                  sram@ffe00000 {

                                                 compatible = "mmio-sram";

                                                 reg = <0xffe00000 0x40000>;

                                  };

     

                                  eccmgr@ffd06000 {

                                                 compatible = "altr,socfpga-a10-ecc-manager";

                                                 altr,sysmgr-syscon = <0x18>;

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x1>;

                                                 interrupts = <0x0 0x2 0x4 0x0 0x0 0x4>;

                                                 interrupt-controller;

                                                 #interrupt-cells = <0x2>;

                                                 ranges;

     

                                                 sdramedac {

                                                                compatible = "altr,sdram-edac-a10";

                                                                altr,sdr-syscon = <0x20>;

                                                                interrupts = <0x11 0x4 0x31 0x4>;

                                                 };

     

                                                 l2-ecc@ffd06010 {

                                                                compatible = "altr,socfpga-a10-l2-ecc";

                                                                reg = <0xffd06010 0x4>;

                                                                interrupts = <0x0 0x4 0x20 0x4>;

                                                 };

     

                                                 ocram-ecc@ff8c3000 {

                                                                compatible = "altr,socfpga-a10-ocram-ecc";

                                                                reg = <0xff8c3000 0x400>;

                                                                interrupts = <0x1 0x4 0x21 0x4>;

                                                 };

     

                                                 emac0-rx-ecc@ff8c0800 {

                                                                compatible = "altr,socfpga-eth-mac-ecc";

                                                                reg = <0xff8c0800 0x400>;

                                                                altr,ecc-parent = <0x21>;

                                                                interrupts = <0x4 0x4 0x24 0x4>;

                                                 };

     

                                                 emac0-tx-ecc@ff8c0c00 {

                                                                compatible = "altr,socfpga-eth-mac-ecc";

                                                                reg = <0xff8c0c00 0x400>;

                                                                altr,ecc-parent = <0x21>;

                                                                interrupts = <0x5 0x4 0x25 0x4>;

                                                 };

     

                                                 dma-ecc@ff8c8000 {

                                                                compatible = "altr,socfpga-dma-ecc";

                                                                reg = <0xff8c8000 0x400>;

                                                                altr,ecc-parent = <0x1b>;

                                                                interrupts = <0xa 0x4 0x2a 0x4>;

                                                 };

     

                                                 usb0-ecc@ff8c8800 {

                                                                compatible = "altr,socfpga-usb-ecc";

                                                                reg = <0xff8c8800 0x400>;

                                                                altr,ecc-parent = <0x22>;

                                                                interrupts = <0x2 0x4 0x22 0x4>;

                                                 };

                                  };

     

                                  spi@ff809000 {

                                                 compatible = "cdns,qspi-nor";

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x0>;

                                                 reg = <0xff809000 0x100 0xffa00000 0x100000>;

                                                 interrupts = <0x0 0x64 0x4>;

                                                 cdns,fifo-depth = <0x80>;

                                                 cdns,fifo-width = <0x4>;

                                                 cdns,trigger-address = <0x0>;

                                                 clocks = <0x23>;

                                                 status = "disabled";

                                  };

     

                                  rstmgr@ffd05000 {

                                                 #reset-cells = <0x1>;

                                                 compatible = "altr,rst-mgr";

                                                 reg = <0xffd05000 0x100>;

                                                 altr,modrst-offset = <0x20>;

                                                 linux,phandle = <0x19>;

                                                 phandle = <0x19>;

                                  };

     

                                  snoop-control-unit@ffffc000 {

                                                 compatible = "arm,cortex-a9-scu";

                                                 reg = <0xffffc000 0x100>;

                                  };

     

                                  sysmgr@ffd06000 {

                                                 compatible = "altr,sys-mgr", "syscon";

                                                 reg = <0xffd06000 0x300>;

                                                 cpu1-start-addr = <0xffd06230>;

                                                 linux,phandle = <0x18>;

                                                 phandle = <0x18>;

                                  };

     

                                  timer@ffffc600 {

                                                 compatible = "arm,cortex-a9-twd-timer";

                                                 reg = <0xffffc600 0x100>;

                                                 interrupts = <0x1 0xd 0xf04>;

                                                 clocks = <0x24>;

                                  };

     

                                  timer0@ffc02700 {

                                                 compatible = "snps,dw-apb-timer";

                                                 interrupts = <0x0 0x73 0x4>;

                                                 reg = <0xffc02700 0x100>;

                                                 clocks = <0x1a>;

                                                 clock-names = "timer";

                                  };

     

                                  timer1@ffc02800 {

                                                 compatible = "snps,dw-apb-timer";

                                                 interrupts = <0x0 0x74 0x4>;

                                                 reg = <0xffc02800 0x100>;

                                                 clocks = <0x1a>;

                                                 clock-names = "timer";

                                  };

     

                                  timer2@ffd00000 {

                                                 compatible = "snps,dw-apb-timer";

                                                 interrupts = <0x0 0x75 0x4>;

                                                 reg = <0xffd00000 0x100>;

                                                 clocks = <0x25>;

                                                 clock-names = "timer";

                                  };

     

                                  timer3@ffd00100 {

                                                 compatible = "snps,dw-apb-timer";

                                                 interrupts = <0x0 0x76 0x4>;

                                                 reg = <0xffd01000 0x100>;

                                                 clocks = <0x25>;

                                                 clock-names = "timer";

                                  };

     

                                  serial0@ffc02000 {

                                                 compatible = "snps,dw-apb-uart";

                                                 reg = <0xffc02000 0x100>;

                                                 interrupts = <0x0 0x6e 0x4>;

                                                 reg-shift = <0x2>;

                                                 reg-io-width = <0x4>;

                                                 clocks = <0x1a>;

                                                 status = "disabled";

                                  };

     

                                  serial1@ffc02100 {

                                                 compatible = "snps,dw-apb-uart";

                                                 reg = <0xffc02100 0x100>;

                                                 interrupts = <0x0 0x6f 0x4>;

                                                 reg-shift = <0x2>;

                                                 reg-io-width = <0x4>;

                                                 clocks = <0x1a>;

                                                 status = "okay";

                                  };

     

                                  usbphy@0 {

                                                 #phy-cells = <0x0>;

                                                 compatible = "usb-nop-xceiv";

                                                 status = "okay";

                                                 linux,phandle = <0x27>;

                                                 phandle = <0x27>;

                                  };

     

                                  usb@ffb00000 {

                                                 compatible = "snps,dwc2";

                                                 reg = <0xffb00000 0xffff>;

                                                 interrupts = <0x0 0x5f 0x4>;

                                                 clocks = <0x26>;

                                                 clock-names = "otg";

                                                 resets = <0x19 0x23>;

                                                 reset-names = "dwc2";

                                                 phys = <0x27>;

                                                 phy-names = "usb2-phy";

                                                 status = "okay";

                                                 linux,phandle = <0x22>;

                                                 phandle = <0x22>;

                                  };

     

                                  usb@ffb40000 {

                                                 compatible = "snps,dwc2";

                                                 reg = <0xffb40000 0xffff>;

                                                 interrupts = <0x0 0x60 0x4>;

                                                 clocks = <0x26>;

                                                 clock-names = "otg";

                                                 resets = <0x19 0x24>;

                                                 reset-names = "dwc2";

                                                 phys = <0x27>;

                                                 phy-names = "usb2-phy";

                                                 status = "disabled";

                                  };

     

                                  watchdog@ffd00200 {

                                                 compatible = "snps,dw-wdt";

                                                 reg = <0xffd00200 0x100>;

                                                 interrupts = <0x0 0x77 0x4>;

                                                 clocks = <0x25>;

                                                 status = "okay";

                                  };

     

                                  watchdog@ffd00300 {

                                                 compatible = "snps,dw-wdt";

                                                 reg = <0xffd00300 0x100>;

                                                 interrupts = <0x0 0x78 0x4>;

                                                 clocks = <0x25>;

                                                 status = "disabled";

                                  };

     

                                  bridge@ff200000 {

                                                 compatible = "simple-bus";

                                                 reg = <0xff200000 0x200000>;

                                                 #address-cells = <0x1>;

                                                 #size-cells = <0x1>;

                                                 ranges = <0x0 0xff200000 0x200000>;

     

                                                 gpio@20 {

                                                                compatible = "altr,pio-1.0";

                                                                reg = <0x20 0x10>;

                                                                altr,gpio-bank-width = <0x20>;

                                                                resetvalue = <0x0>;

                                                                #gpio-cells = <0x2>;

                                                                gpio-controller;

                                                                linux,phandle = <0x28>;

                                                                phandle = <0x28>;

                                                 };

     

                                                 spi@40 {

                                                                compatible = "altr,spi-1.0";

                                                                reg = <0x40 0x20>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x1a 0x4>;

                                                                #address-cells = <0x1>;

                                                                #size-cells = <0x0>;

     

                                                                ad9528-1@0 {

                                                                               #address-cells = <0x1>;

                                                                               #size-cells = <0x0>;

                                                                               #clock-cells = <0x1>;

                                                                               compatible = "ad9528";

                                                                               spi-max-frequency = <0x989680>;

                                                                               reg = <0x0>;

                                                                               clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";

                                                                               adi,vcxo-freq = <0x4c4b400>;

                                                                               adi,refa-enable;

                                                                               adi,refa-diff-rcv-enable;

                                                                               adi,refa-r-div = <0x1>;

                                                                               adi,osc-in-cmos-neg-inp-enable;

                                                                               adi,pll1-feedback-div = <0x4>;

                                                                               adi,pll1-charge-pump-current-nA = <0x1388>;

                                                                               adi,pll2-vco-div-m1 = <0x4>;

                                                                               adi,pll2-n2-div = <0xc>;

                                                                               adi,pll2-r1-div = <0x1>;

                                                                               adi,pll2-charge-pump-current-nA = <0xc4888>;

                                                                               adi,sysref-src = <0x2>;

                                                                               adi,sysref-pattern-mode = <0x1>;

                                                                               adi,sysref-k-div = <0x200>;

                                                                               adi,sysref-request-enable;

                                                                               adi,sysref-nshot-mode = <0x3>;

                                                                               adi,sysref-request-trigger-mode = <0x0>;

                                                                               adi,rpole2 = <0x0>;

                                                                               adi,rzero = <0x7>;

                                                                               adi,cpole1 = <0x2>;

                                                                               adi,status-mon-pin0-function-select = <0x1>;

                                                                               adi,status-mon-pin1-function-select = <0x7>;

                                                                               reset-gpios = <0x28 0x1b 0x0>;

                                                                               linux,phandle = <0x2c>;

                                                                               phandle = <0x2c>;

     

                                                                               channel@13 {

                                                                                              reg = <0xd>;

                                                                                              adi,extended-name = "DEV_CLK";

                                                                                              adi,driver-mode = <0x0>;

                                                                                              adi,divider-phase = <0x0>;

                                                                                              adi,channel-divider = <0x3>;

                                                                                              adi,signal-source = <0x0>;

                                                                               };

     

                                                                               channel@1 {

                                                                                              reg = <0x1>;

                                                                                              adi,extended-name = "FMC_CLK";

                                                                                              adi,driver-mode = <0x0>;

                                                                                              adi,divider-phase = <0x0>;

                                                                                              adi,channel-divider = <0x3>;

                                                                                              adi,signal-source = <0x0>;

                                                                               };

     

                                                                               channel@12 {

                                                                                              reg = <0xc>;

                                                                                              adi,extended-name = "DEV_SYSREF";

                                                                                              adi,driver-mode = <0x0>;

                                                                                              adi,divider-phase = <0x0>;

                                                                                              adi,channel-divider = <0x3>;

                                                                                              adi,signal-source = <0x2>;

                                                                               };

     

                                                                               channel@3 {

                                                                                              reg = <0x3>;

                                                                                              adi,extended-name = "FMC_SYSREF";

                                                                                              adi,driver-mode = <0x0>;

                                                                                              adi,divider-phase = <0x0>;

                                                                                              adi,channel-divider = <0x3>;

                                                                                              adi,signal-source = <0x2>;

                                                                               };

                                                                };

     

                                                                ad9371-phy@1 {

                                                                               #address-cells = <0x1>;

                                                                               #size-cells = <0x0>;

                                                                               #clock-cells = <0x1>;

                                                                               compatible = "ad9371";

                                                                               reg = <0x1>;

                                                                               spi-max-frequency = <0x17d7840>;

                                                                               clocks = <0x29 0x2a 0x2b 0x2c 0xd 0x2c 0x1>;

                                                                               clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk";

                                                                               clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";

                                                                               adi,clocks-clk-pll-vco-freq_khz = <9600000>;

                                                                               adi,clocks-device-clock_khz = <320000>;

                                                                               adi,clocks-clk-pll-hs-div = <0x4>;

                                                                               adi,clocks-clk-pll-vco-div = <0x3>;

                                                                               adi,jesd204-obs-framer-over-sample = <0x0>;

                                                                               adi,rx-profile-adc-div = <0x1>;

                                                                               adi,rx-profile-en-high-rej-dec5 = <0x1>;

                                                                               adi,rx-profile-iq-rate_khz = <0x13880>;

                                                                               adi,rx-profile-rf-bandwidth_hz = <0x2625a00>;

                                                                               adi,rx-profile-rhb1-decimation = <0x1>;

                                                                               adi,rx-profile-rx-bbf-3db-corner_khz = <0x9c40>;

                                                                               adi,rx-profile-rx-dec5-decimation = <0x5>;

                                                                               adi,rx-profile-rx-fir-decimation = <0x2>;

                                                                               adi,rx-profile-rx-fir-gain_db = <(-6)>;

                                                                               adi,rx-profile-rx-fir-num-fir-coefs = <48>;

                                                                               adi,rx-profile-rx-fir-coefs = <(1) (7) (3) (-20) (-38) (10) (107) (100) (-122) (-334) (-113) (506) (718) (-166) (-1391) (-1095) (1231) (3033) (981) (-4224) (-6482) (219) (14325) (26107) (26107) (14325) (219) (-6482) (-4224) (981) (3033) (1231) (-1095) (-1391) (-166) (718) (506) (-113) (-334) (-122) (100) (107) (10) (-38) (-20) (3) (7) (1)>;

                                                                               adi,rx-profile-custom-adc-profile = <900 559 201 98 1280 199 1522 98 860 25 529 37 48 26 15 196>;

                                                                               adi,obs-profile-adc-div = <0x1>;

                                                                               adi,obs-profile-en-high-rej-dec5 = <0x1>;

                                                                               adi,obs-profile-iq-rate_khz = <0x13880>;

                                                                               adi,obs-profile-rf-bandwidth_hz = <0x2625a00>;

                                                                               adi,obs-profile-rhb1-decimation = <0x1>;

                                                                               adi,obs-profile-rx-bbf-3db-corner_khz = <0x4e20>;

                                                                               adi,obs-profile-rx-dec5-decimation = <0x5>;

                                                                               adi,obs-profile-rx-fir-decimation = <0x2>;

                                                                               adi,obs-profile-rx-fir-gain_db = <(-6)>;

                                                                               adi,obs-profile-rx-fir-num-fir-coefs = <48>;

                                                                               adi,obs-profile-rx-fir-coefs = <(-1) (10) (10) (-22) (-60) (-6) (143) (171) (-129) (-485) (-245) (660) (1099) (-74) (-1954) (-1784) (1506) (4443) (1920) (-5737) (-10210) (-2631) (15550) (31189) (31189) (15550) (-2631) (-10210) (-5737) (1920) (4443) (1506) (-1784) (-1954) (-74) (1099) (660) (-245) (-485) (-129) (171) (143) (-6) (-60) (-22) (10) (10) (-1)>;

                                                                               adi,obs-profile-custom-adc-profile = <900 559 201 98 1280 199 1522 98 860 25 529 37 48 26 15 196>;

                                                                               adi,obs-settings-custom-loopback-adc-profile = <922 550 201 98 1280 112 1505 53 864 14 533 40 48 26 15 197>;

                                                                               adi,tx-profile-dac-div = <0x1>;

                                                                               adi,tx-profile-iq-rate_khz = <0x13880>;

                                                                               adi,tx-profile-primary-sig-bandwidth_hz = <0x1312d00>;

                                                                               adi,tx-profile-rf-bandwidth_hz = <0x2625a00>;

                                                                               adi,tx-profile-thb1-interpolation = <0x2>;

                                                                               adi,tx-profile-thb2-interpolation = <0x2>;

                                                                               adi,tx-profile-tx-bbf-3db-corner_khz = <0x4e20>;

                                                                               adi,tx-profile-tx-dac-3db-corner_khz = <0x16760>;

                                                                               adi,tx-profile-tx-fir-interpolation = <0x1>;

                                                                               adi,tx-profile-tx-input-hb-interpolation = <0x1>;

                                                                               adi,tx-profile-tx-fir-gain_db = <6>;

                                                                               adi,tx-profile-tx-fir-num-fir-coefs = <16>;

                                                                               adi,tx-profile-tx-fir-coefs = <26 (-292) (-75) 333 339 (-659) (-2192) 21034 (-2192) (-659) 339 333 (-75) (-292) 26 0>;

                                                                               adi,sniffer-profile-adc-div = <0x1>;

                                                                               adi,sniffer-profile-en-high-rej-dec5 = <0x1>;

                                                                               adi,sniffer-profile-iq-rate_khz = <0x9c40>;

                                                                               adi,sniffer-profile-rf-bandwidth_hz = <0x1312d00>;

                                                                               adi,sniffer-profile-rhb1-decimation = <0x2>;

                                                                               adi,sniffer-profile-rx-bbf-3db-corner_khz = <0x4e20>;

                                                                               adi,sniffer-profile-rx-dec5-decimation = <0x5>;

                                                                               adi,sniffer-profile-rx-fir-decimation = <0x2>;

                                                                               adi,sniffer-profile-rx-fir-gain_db = <(-6)>;

                                                                               adi,sniffer-profile-rx-fir-num-fir-coefs = <72>;

                                                                               adi,sniffer-profile-rx-fir-coefs = <(-9) (12) (18) (17) (-17) (-49) (-45) (21) (99) (105) (-11) (-171) (-215) (-36) (258) (390) (149) (-343) (-648) (-371) (394) (1003) (763) (-357) (-1476) (-1425) (138) (2113) (2589) (489) (-3082) (-5079) (-2537) (4990) (14500) (21095) (21095) (14500) (4990) (-2537) (-5079) (-3082) (489) (2589) (2113) (138) (-1425) (-1476) (-357) (763) (1003) (394) (-371) (-648) (-343) (149) (390) (258) (-36) (-215) (-171) (-11) (105) (99) (21) (-45) (-49) (-17) (17) (18) (12) (-9)>;

                                                                               adi,sniffer-profile-custom-adc-profile = <922 550 201 98 1280 112 1505 53 864 14 533 40 48 26 15 197>;

                                                                               reset-gpios = <0x28 0x14 0x0>;

                                                                               test-gpios = <0x28 0x15 0x0>;

                                                                               sysref_req-gpios = <0x28 0x1a 0x0>;

                                                                               rx2_enable-gpios = <0x28 0x16 0x0>;

                                                                               rx1_enable-gpios = <0x28 0x17 0x0>;

                                                                               tx2_enable-gpios = <0x28 0x18 0x0>;

                                                                               tx1_enable-gpios = <0x28 0x19 0x0>;

                                                                               linux,phandle = <0x36>;

                                                                               phandle = <0x36>;

                                                                };

                                                 };

     

                                                 axi-jesd204-tx@20000 {

                                                                compatible = "adi,axi-jesd204-tx-1.0";

                                                                reg = <0x20000 0x4000>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x1c 0x0>;

                                                                clocks = <0x2d 0x2e 0x2f>;

                                                                clock-names = "s_axi_aclk", "device_clk", "lane_clk";

                                                                adi,octets-per-frame = <0x2>;

                                                                adi,frames-per-multiframe = <0x20>;

                                                                adi,converter-resolution = <0xe>;

                                                                adi,bits-per-sample = <0x10>;

                                                                adi,converters-per-device = <0x4>;

                                                                adi,control-bits-per-sample = <0x2>;

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd_tx_lane_clk";

                                                                linux,phandle = <0x2a>;

                                                                phandle = <0x2a>;

                                                 };

     

                                                 axi-jesd204-rx@30000 {

                                                                compatible = "adi,axi-jesd204-rx-1.0";

                                                                reg = <0x30000 0x4000>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x1b 0x0>;

                                                                clocks = <0x2d 0x30 0x31>;

                                                                clock-names = "s_axi_aclk", "device_clk", "lane_clk";

                                                                adi,octets-per-frame = <0x4>;

                                                                adi,frames-per-multiframe = <0x20>;

                                                                adi,converter-resolution = <0x10>;

                                                                adi,bits-per-sample = <0x10>;

                                                                adi,converters-per-device = <0x4>;

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd_rx_lane_clk";

                                                                linux,phandle = <0x29>;

                                                                phandle = <0x29>;

                                                 };

     

                                                 axi-jesd204-rx@40000 {

                                                                compatible = "adi,axi-jesd204-rx-1.0";

                                                                reg = <0x40000 0x4000>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x1d 0x0>;

                                                                clocks = <0x2d 0x32 0x33>;

                                                                clock-names = "s_axi_aclk", "device_clk", "lane_clk";

                                                                adi,octets-per-frame = <0x2>;

                                                                adi,frames-per-multiframe = <0x20>;

                                                                adi,converter-resolution = <0x10>;

                                                                adi,bits-per-sample = <0x10>;

                                                                adi,converters-per-device = <0x4>;

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd_rx_os_lane_clk";

                                                                linux,phandle = <0x2b>;

                                                                phandle = <0x2b>;

                                                 };

     

                                                 axi-ad9371-tx-xcvr@24000 {

                                                                compatible = "adi,altera-adxcvr-1.00.a";

                                                                reg = <0x24000 0x1000 0x26000 0x1000 0x28000 0x1000 0x29000 0x1000 0x2a000 0x1000 0x2b000 0x1000>;

                                                                reg-names = "adxcvr", "atx-pll", "adxcfg-0", "adxcfg-1", "adxcfg-2", "adxcfg-3";

                                                                clocks = <0x2c 0x1 0x2e>;

                                                                clock-names = "ref", "link";

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd204_tx_lane_clock";

                                                                linux,phandle = <0x2f>;

                                                                phandle = <0x2f>;

                                                 };

     

                                                 axi-ad9371-rx-xcvr@34000 {

                                                                compatible = "adi,altera-adxcvr-1.00.a";

                                                                reg = <0x34000 0x1000 0x38000 0x1000 0x39000 0x1000>;

                                                                reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";

                                                                clocks = <0x2c 0x1 0x30>;

                                                                clock-names = "ref", "link";

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd204_rx_lane_clock";

                                                                linux,phandle = <0x31>;

                                                                phandle = <0x31>;

                                                 };

     

                                                 axi-ad9371-rx-os-xcvr@44000 {

                                                                compatible = "adi,altera-adxcvr-1.00.a";

                                                                reg = <0x44000 0x1000 0x48000 0x1000 0x49000 0x1000>;

                                                                reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";

                                                                clocks = <0x2c 0x1 0x32>;

                                                                clock-names = "ref", "link";

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd204_rx_os_lane_clock";

                                                                linux,phandle = <0x33>;

                                                                phandle = <0x33>;

                                                 };

     

                                                 axi-ad9371-tx-dma@2c000 {

                                                                compatible = "adi,axi-dmac-1.00.a";

                                                                reg = <0x2c000 0x4000>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x1e 0x4>;

                                                                #dma-cells = <0x1>;

                                                                clocks = <0x34>;

                                                                linux,phandle = <0x37>;

                                                                phandle = <0x37>;

     

                                                                dma-channel {

                                                                               adi,source-bus-width = <0x80>;

                                                                               adi,destination-bus-width = <0x80>;

                                                                               adi,type = <0x1>;

                                                                };

                                                 };

     

                                                 axi-ad9371-rx-dma@3c000 {

                                                                compatible = "adi,axi-dmac-1.00.a";

                                                                reg = <0x3c000 0x4000>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x1f 0x4>;

                                                                #dma-cells = <0x1>;

                                                                clocks = <0x34>;

                                                                linux,phandle = <0x35>;

                                                                phandle = <0x35>;

     

                                                                dma-channel {

                                                                               adi,source-bus-width = <0x40>;

                                                                               adi,destination-bus-width = <0x80>;

                                                                               adi,type = <0x0>;

                                                                };

                                                 };

     

                                                 axi-ad9371-rx-os-dma@4c000 {

                                                                compatible = "adi,axi-dmac-1.00.a";

                                                                reg = <0x4c000 0x4000>;

                                                                interrupt-parent = <0x2>;

                                                                interrupts = <0x0 0x20 0x4>;

                                                                #dma-cells = <0x1>;

                                                                clocks = <0x34>;

                                                                linux,phandle = <0x38>;

                                                                phandle = <0x38>;

     

                                                                dma-channel {

                                                                               adi,source-bus-width = <0x40>;

                                                                               adi,destination-bus-width = <0x80>;

                                                                               adi,type = <0x0>;

                                                                };

                                                 };

     

                                                 axi-ad9371-rx-hpc@50000 {

                                                                compatible = "adi,axi-ad9371-rx-1.0";

                                                                reg = <0x50000 0x8000>;

                                                                dmas = <0x35 0x0>;

                                                                dma-names = "rx";

                                                                spibus-connected = <0x36>;

                                                 };

     

                                                 axi-ad9371-tx-hpc@54000 {

                                                                compatible = "adi,axi-ad9371-tx-1.0";

                                                                reg = <0x54000 0x4000>;

                                                                dmas = <0x37 0x0>;

                                                                dma-names = "tx";

                                                                clocks = <0x36 0x2>;

                                                                clock-names = "sampl_clk";

                                                                spibus-connected = <0x36>;

                                                                adi,axi-pl-fifo-enable;

                                                                plddrbypass-gpios = <0x28 0x1c 0x0>;

                                                 };

     

                                                 axi-ad9371-rx-obs-hpc@58000 {

                                                                compatible = "adi,axi-ad9371-obs-1.0";

                                                                reg = <0x58000 0x1000>;

                                                                dmas = <0x38 0x0>;

                                                                dma-names = "rx";

                                                                clocks = <0x36 0x1>;

                                                                clock-names = "sampl_clk";

                                                 };

     

                                                 altera-a10-fpll@25000 {

                                                                compatible = "altr,a10-fpll";

                                                                reg = <0x25000 0x1000>;

                                                                clocks = <0x2c 0x1>;

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd204_tx_link_clock";

                                                                linux,phandle = <0x2e>;

                                                                phandle = <0x2e>;

                                                 };

     

                                                 altera-a10-fpll@35000 {

                                                                compatible = "altr,a10-fpll";

                                                                reg = <0x35000 0x1000>;

                                                                clocks = <0x2c 0x1>;

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd204_rx_link_clock";

                                                                linux,phandle = <0x30>;

                                                                phandle = <0x30>;

                                                 };

     

                                                 altera-a10-fpll@45000 {

                                                                compatible = "altr,a10-fpll";

                                                                reg = <0x45000 0x1000>;

                                                                clocks = <0x2c 0x1>;

                                                                #clock-cells = <0x0>;

                                                                clock-output-names = "jesd204_rx_os_link_clock";

                                                                linux,phandle = <0x32>;

                                                                phandle = <0x32>;

                                                 };

                                  };

                   };

     

                   a10leds {

                                  compatible = "gpio-leds";

     

                                  a10sr_led0 {

                                                 label = "a10sr-led0";

                                                 gpios = <0x39 0x0 0x1>;

                                  };

     

                                  a10sr_led1 {

                                                 label = "a10sr-led1";

                                                 gpios = <0x39 0x1 0x1>;

                                  };

     

                                  a10sr_led2 {

                                                 label = "a10sr-led2";

                                                 gpios = <0x39 0x2 0x1>;

                                  };

     

                                  a10sr_led3 {

                                                 label = "a10sr-led3";

                                                 gpios = <0x39 0x3 0x1>;

                                  };

                   };

     

                   clocks {

     

                                  sys_clk {

                                                 #clock-cells = <0x0>;

                                                 compatible = "fixed-clock";

                                                 clock-frequency = <0x5f5e100>;

                                                 clock-output-names = "system_clock";

                                                 linux,phandle = <0x2d>;

                                                 phandle = <0x2d>;

                                  };

     

                                  dma_clk {

                                                 #clock-cells = <0x0>;

                                                 compatible = "fixed-clock";

                                                 clock-frequency = <0xee6b280>;

                                                 clock-output-names = "dma_clk";

                                                 linux,phandle = <0x34>;

                                                 phandle = <0x34>;

                                  };

     

                                  clock@0 {

                                                 #clock-cells = <0x0>;

                                                 compatible = "fixed-clock";

                                                 clock-frequency = <0x7a1200>;

                                                 clock-output-names = "ad9371_ext_refclk";

                                  };

                   };

    };

  • My sampling rate is 80Msps, but device clock is 320MHz (80MHz *4). It is because JESD links do not “like” sampling rate the same as device clock and work much better at device clock multiple of sampling rate.

    (but calibration is failing at 80MHz device clk as well)

    •  Analog Employees 
    on Jan 22, 2019 10:16 AM in reply to mgaleev

    Tx QEC can fail if matching is not correct or if you are using a very large Tx attenuation setting. Since you are using Eval board matching should be Ok.

    As Michael mentioned , you should use the profile wizard to create custom profile which matches your sampling rate requirement.