AD9371 jesd link problem

Hello,

I have VCU108 Evaluation Kit and ADRV9371-W/PCBZ

I have a working design for the 50 MHz signal bandwidth and the IQ sample rate 61.44 MHz with the following jesd settings:

FPGA side:

  • JTX
    • L = 4 – number of lanes
    • F = 2 – octets per frame
    • K = 32 – frames per multiframe
    • 30.72 MHz – core clock
    • 1.2288 Gbps – lane rate
    • Subclass 1
    • Scrambling off
  • JRX
    • L = 2 – number of lanes
    • F = 4 – octets per frame
    • K = 32 – frames per multiframe
    • 61.44 MHz – core clock
    • 2.4576 Gbps– lane rate
    • Subclass 1
    • Scrambling off

AD9371side:

  • JTX (Framer)
    • L = 2 – number of lanes
    • K = 32 – frames per multiframe (default=32). F*K must be a multiple of 4. (F=2*M/L)
    • M = 4 – number of ADCs (0, 2, or 4) - 2 ADCs per receive chain
    • F = 4 – octets per frame
    • 61.44 MHz – IQ data rate
    • 1.2288 Gbps – lane rate (Lane Rate = IQ Sample Rate × M × 16 bits × (10 ÷ 8) ÷ L)
    • Subclass 1
    • Scrambling off
  • JRX (Deframer)
    • L = 4 – number of lanes
    • K = 32 – frames per multiframe (default=32). F*K must be a multiple of 4. (F=2*M/L)
    • M = 4 – number of DACs (0, 2, or 4) - 2 DACs per transmit chain
    • F = 2 – octets per frame
    • 61.44 MHz – IQ data rate
    • 2.4576 Gbps – lane rate (Lane Rate = IQ Sample Rate × M × 16 bits × (10 ÷ 8) ÷ L)
    • Subclass 1
    • Scrambling off

Now i need increase the bandwidth to 80 MHz and the IQ rate to 122.88 MHz. I changed the core clock and lane rate on the FPGA side by doubling them for JTX and JRX, respectively.On the AD9371 side the IQ data rate was changed from 61.44 MHz to 122.88 MHz. Bandwidth and Filters settings was changed, these values were taken from AD9371 Filter Wizard.

Now we have problems with establishing a jesd connection in both directions. SYNC toggles occasionally.

What am I doing wrong?