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AD9371 jesd link problem

Hello,

I have VCU108 Evaluation Kit and ADRV9371-W/PCBZ

I have a working design for the 50 MHz signal bandwidth and the IQ sample rate 61.44 MHz with the following jesd settings:

FPGA side:

  • JTX
    • L = 4 – number of lanes
    • F = 2 – octets per frame
    • K = 32 – frames per multiframe
    • 30.72 MHz – core clock
    • 1.2288 Gbps – lane rate
    • Subclass 1
    • Scrambling off
  • JRX
    • L = 2 – number of lanes
    • F = 4 – octets per frame
    • K = 32 – frames per multiframe
    • 61.44 MHz – core clock
    • 2.4576 Gbps– lane rate
    • Subclass 1
    • Scrambling off

AD9371side:

  • JTX (Framer)
    • L = 2 – number of lanes
    • K = 32 – frames per multiframe (default=32). F*K must be a multiple of 4. (F=2*M/L)
    • M = 4 – number of ADCs (0, 2, or 4) - 2 ADCs per receive chain
    • F = 4 – octets per frame
    • 61.44 MHz – IQ data rate
    • 1.2288 Gbps – lane rate (Lane Rate = IQ Sample Rate × M × 16 bits × (10 ÷ 8) ÷ L)
    • Subclass 1
    • Scrambling off
  • JRX (Deframer)
    • L = 4 – number of lanes
    • K = 32 – frames per multiframe (default=32). F*K must be a multiple of 4. (F=2*M/L)
    • M = 4 – number of DACs (0, 2, or 4) - 2 DACs per transmit chain
    • F = 2 – octets per frame
    • 61.44 MHz – IQ data rate
    • 2.4576 Gbps – lane rate (Lane Rate = IQ Sample Rate × M × 16 bits × (10 ÷ 8) ÷ L)
    • Subclass 1
    • Scrambling off

Now i need increase the bandwidth to 80 MHz and the IQ rate to 122.88 MHz. I changed the core clock and lane rate on the FPGA side by doubling them for JTX and JRX, respectively.On the AD9371 side the IQ data rate was changed from 61.44 MHz to 122.88 MHz. Bandwidth and Filters settings was changed, these values were taken from AD9371 Filter Wizard.

Now we have problems with establishing a jesd connection in both directions. SYNC toggles occasionally.

What am I doing wrong?

  • Can you check the JESD framer and deframer status by using the following API:

    MYKONOS_readRxFramerStatus

    MYKONOS_readDeframerStatus

  • The Framer status 0x20:

    • Framer has received the SYSREF and has retimed its LMFC
    • ILAS state - CGS
    • Tx state - CGS

    or another Framer status 0x25:

    • Framer has received the SYSREF and has retimed its LMFC
    • ILAS state - 1st Multiframe
    • Tx state - ILAS


    The Deframer status 0X61:

    • Deframer IRQ
    • Deframer SYSREF Received
    • FS Lost

    or another Deframer status 0x60:

    • Deframer IRQ
    • Deframer SYSREF Received

    But if I do a reinitialization of the ad9371 the Framer status can change to 0x60 or 0x65.

  • This looks to be a signal integrity issue as you are not observing the issue with lower datarates.

    For general guidelines on JESD debugging you can refer to the following link:

    https://ez.analog.com/wide-band-rf-transceivers/design-support-ad9371/w/documents/13976/jesd-debugging

  • Hello srimoyi,

    Can you brief on signal integrity issue and methods to resolve them. 

    I having almost same problem.

    I getting JESD link errors

    Thank you

    Pavan

  • You can use PRBS checker and generator to confirm the signal integrity of the link. Refer to the link shared above for steps to do so.

    https://en.wikipedia.org/wiki/Signal_integrity

  • when you change sampling rate you need to use the profile wizard to create new profile and load that or replace initdata.c file.

    https://wiki.analog.com/resources/eval/user-guides/mykonos/software/filters

  • Hello Thanks for suggesting the links,

    In have checked using PRBS checker but giving large values.

    This is my current status in teraterm

    Please wait...
    rx_clkgen: MMCM-PLL locked (122880000 Hz)
    tx_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
    MCS successful
    CLKPLL locked
    AD9371 ARM version 5.2.2
    PLLs locked
    Calibrations completed successfully
    tx_adxcvr: OK (4915200 kHz)
    rx_adxcvr: OK (4915200 kHz)
    rx_os_adxcvr: OK (4915200 kHz)
    RxFramerStatus = 0x7e                              //Sometimes it will change to 0xbe
    OrxFramerStatus = 0x20
    DeframerStatus = 0x21                              // Sometimes it will change to 0x60
    DeframerPrbsCounters=94594
    rx_jesd: Lane 0 desynced (125 errors), restarting link
    rx_jesd: Lane 1 desynced (57 errors), restarting link
    rx_os_jesd: Lane 0 desynced (178198 errors), restarting link
    rx_os_jesd: Lane 1 desynced (154567 errors), restarting link
    rx_jesd status:
    Link is enabled
    Measured Link Clock: 122.881 MHz
    Reported Link Clock: 122.880 MHz
    Lane rate: 4915.200 MHz
    Lane rate / 40: 122.880 MHz
    Link status: CGS
    SYSREF captured: Yes
    SYSREF alignment error: Yes
    rx_jesd lane 0 status:
    Errors: 0
    CGS state: INIT
    Initial Frame Synchronization: No
    rx_jesd lane 1 status:
    Errors: 0
    CGS state: INIT
    Initial Frame Synchronization: No
    tx_jesd status:
    Link is enabled
    Measured Link Clock: 122.882 MHz
    Reported Link Clock: 122.880 MHz
    Lane rate: 4915.200 MHz
    Lane rate / 40: 122.880 MHz
    SYNC~: deasserted
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment error: Yes
    rx_os_jesd status:
    Link is enabled
    Measured Link Clock: 122.881 MHz
    Reported Link Clock: 122.880 MHz
    Lane rate: 4915.200 MHz
    Lane rate / 40: 122.880 MHz
    Link status: CGS
    SYSREF captured: Yes
    SYSREF alignment error: Yes
    rx_os_jesd lane 0 status:
    Errors: 0
    CGS state: INIT
    Initial Frame Synchronization: No
    rx_os_jesd lane 1 status:
    Errors: 0
    CGS state: INIT
    Initial Frame Synchronization: No
    tx_dac: Successfully initialized (245764160 Hz)
    rx_adc: Successfully initialized (122880554 Hz)
    rx_obs_adc: Successfully initialized (245761108 Hz)
    Done

    Note: I am integrating KCU116 with ADRV9371 board. (It is not supported carrier as mentioned by ADI)

    But I need this in my project 

    Please tell me what is mistake i am doing here

    Thank you

    Pavan

  • Are you using custom board or eval board? Can you check the status of the sync_in signal? Maks sure that your ref_clk is clean and jitter free.

  • Hello Srimoyi,

    I am using Kintex ultrascale plus board (KCU116) with AD9371.

    My ref_clk is from 30.72 MHz +5.00 dBm. (External signal synthesizer)

    sync_in -> you mean tapping point?

    What should be the nature of this pin?

    Thank you

    Regards

    Pavan

  • Refer to the  "HARDWARE CONSIDERATIONS FOR SYNC SIGNALS" section in UG for details on this pin.

    Refer to the JESD debug document shared earlier for the function of this pin