I have VCU108 Evaluation Kit and ADRV9371-W/PCBZ
I have a working design for the 50 MHz signal bandwidth and the IQ sample rate 61.44 MHz with the following jesd settings:
Now i need increase the bandwidth to 80 MHz and the IQ rate to 122.88 MHz. I changed the core clock and lane rate on the FPGA side by doubling them for JTX and JRX, respectively.On the AD9371 side the IQ data rate was changed from 61.44 MHz to 122.88 MHz. Bandwidth and Filters settings was changed, these values were taken from AD9371 Filter Wizard.
Now we have problems with establishing a jesd connection in both directions. SYNC toggles occasionally.
What am I doing wrong?
Can you check the JESD framer and deframer status by using the following API:
The Framer status 0x20:
or another Framer status 0x25:
The Deframer status 0X61:
or another Deframer status 0x60:
But if I do a reinitialization of the ad9371 the Framer status can change to 0x60 or 0x65.
This looks to be a signal integrity issue as you are not observing the issue with lower datarates.
For general guidelines on JESD debugging you can refer to the following link: