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ADRF6755  jitter  At the noise floor

Hi ,

When I debug ADRF6755's PLL, I meet two issues . When I configure  Frac-N PLL output 2400MHz (PFD =40MHz):

1) The random spurs is  dynamic .

2)  The noise floor  fluctuate .

 The issue  is described in accessory document . I  can't resolve and make it clearly. Please give me a help.
  • The moving noise/moving spur you are seeing on the ADRF6755 is normal. We call it a "wandering spur". It is inherent in the high-order (2^25) sigma-delta modulator. It is a spur whose offset from the carrier changes over time. Depending on what instrument you use to look at it, it appears as a spur sweeping across the screen, or as phase noise ‘breathing’ up and down. It is seen on the ADF4157, ADF4158, and ADF4159 (and similar competitor parts). It appears worst around the integer boundary frequencies.

    We may be able to help you reduce this effect depending on your configuration but I need to ask some more questions:

    Please provide the following:

    • Reference frequency
    • reference path setup (doubler, divide-by-2 and 5-bit r divider settings)
    • Charge pump current setting (CR9 [7:4])
  • Hi,LKelly:

               Thanks for your reply , your  explain prove my guess,but I didn't  thought  the "wandering spur"  was  so   high and  powerful.   The configure that you concern  is  configured as below : 

    • Reference frequency     40MHz     and    fPFD  = 40 MHz
    • reference path setup     Bypass Double   divide-by-2 and 5-bit r divider settings  (the  three modules  either bypass or unable )
    • Charge pump current setting (CR9 [7:4])          I set max CP current 

             Then,except   Reference frequency and fPFD ,  I  have  changed the configure of  the  reference path setup  and cp current ,but it  didn't have effection.

             Look  forward to your suggestion.



                                                                                                       XJ Lee                                                                                                                              

  • Hi,LKelly:

               I have some issues  to  supple .

                       1)   I want to know    how low  the   "wandering spur" can be restrained . I want it  lower than   -65dBc . Can it                                   be   achieved ?

                           2)   Can you recommend some materials about   sigma-delta modulator of PLL . I want to know its principle. The more                                detail ,the better .

                         Look  forward to your good information.



                                                                                                       XJ Lee  

  • Please write CR19=0x96 (instead of the default value of 0x80)

    I believe this should reduce or eliminate the wandering spur in the case where FRAC=0.

    There is an old presentation here you might find useful:

    These are our general tutorials on PLLs:

  • Hi,LKelly:

             I have do it as you said that write CR19=0x96, it works effectively  and the  "wandering spur"  has  eliminated at the frequence of  Int-N (for example  2400MHz with fPFD = 40MHz) and Frac-N .But at the same time,   stable spur is appeared at the frequence of Frac-N(for example 1875MHz with fPFD = 40MHz ) .The stable spur  is about lower  45dB than the signal of LO. I try to change the data of  CR19 arbitrarily .It doesn't work again .  I upload three pictures  about this phenomenon .

            Can you introduce the CR19 Register's function ?  Does it regulate dithering ?  Please give me some suggestions . Can you give me the related Regisrers's  describtion which is not described in the datasheet   if it possible.

            Look forward to your suggestions.



                                                                                                       XJ Lee






  • I don't see such a spur with any value in CR19. This might be noise coming from your power supply. Try changing to a different supply and observing if the spur disappears or changes to another frequency.

    Setting CR19=0x96 disables the SDM when FRAC=0 (when the SDM is not needed). It will not provide any benefit to spurs when FRAC is not zero.

    The register settings I used for LO=1875MHz, Ref=PFD=40MHz are below. I did not see any spur at 10kHz offset.

    CR0 0
    CR1 0
    CR2 C0
    CR3 5
    CR4 1
    CR5 0
    CR6 2E
    CR7 0
    CR8 0
    CR9 F0
    CR10 1
    CR11 0
    CR12 18
    CR13 E8
    CR14 80
    CR15 0
    CR16 0
    CR17 0
    CR18 60
    CR19 80
    CR20 0
    CR21 0
    CR22 80
    CR23 70
    CR24 18
    CR25 64
    CR26 0
    CR27 17
    CR28 8
    CR29 80
    CR30 0
  • Hi,LKelly:

           I misunderstand your  expression previously. Now,  It's clear  at the frequence of  Int-N and the"wander spurs" is -55dBc lower than LO signal  at the frequence of  Frac-N.

          Thank you for your help very much . I know ADRF6755 more well through your help .  Thanks again.




                                                                                                       XJ Lee

  • You're very welcome. Good luck with your project.