Dear Analog Devices Technical Support Team,
We are developing a multi-frequency bio-impedance measurement system using an AD5940 BIOZ evaluation board controlled by an Atmosic ATM3405 MCU through SPI.
SPI communication and interrupt operation have been verified successfully:
- ADIID: 0x4144
- CHIPID: 0x5502
- AD5940 silicon revision: S3
- GP0 FIFO interrupt: operating correctly
- SPI communication: stable
- AD5940_Initialize(): completed successfully
Our firmware is based on the Analog Devices AD5940 Body Impedance example and the AD5940 library.
Hardware configuration
- AD5940 BIOZ evaluation board
- AD5940 Z Test Board
- Four-wire BIA configuration
- Z Test Board switches:
- S1-5: OFF
- S1-12: OFF
- All other S1 switches: ON
- S2 through S5: ON
- Nominal test impedance: approximately 510 Ω in series with 10 nF
The expected impedance is approximately:
- 50 kHz: 601 Ω, −32°
- 200 kHz: 516 Ω, −8.9°
Known-good 50 kHz result
Using the original two-DFT-pair BIA measurement sequence, we obtained the following stable result:
- Frequency: 50 kHz
- HSTIA RTIA: 1 kΩ
- ADC PGA: ×1
- Excitation setting: 800 mVpp
- ADC clock: 16 MHz
- Measured impedance: 612.0 Ω
- Measured phase: −31.68°
This result closely agrees with the expected value of the Z Test Board.
Problem at 200 kHz
When increasing the measurement frequency to 200 kHz, the measured impedance and phase become incorrect. Depending on the diagnostic configuration, typical results are:
- Magnitude: approximately 29 kΩ to 33 kΩ
- Phase: approximately −92°
- Current DFT magnitude: only approximately 3 to 30 counts
- Voltage DFT magnitude: changes normally and linearly with excitation amplitude
The voltage DFT responds correctly when the excitation amplitude is changed. For example, with PGA ×4:
- 50 mVpp: VM ≈ 86
- 100 mVpp: VM ≈ 173
- 200 mVpp: VM ≈ 345
Changing from 200 mVpp/PGA ×4 to 400 mVpp/PGA ×1 produces approximately half the ADC voltage magnitude, as expected.
Therefore, the waveform generator, voltage ADC channel, PGA switching, DFT processing and FIFO update appear to be operating correctly.
However, the current DFT remains much smaller than expected and its phase is displaced by approximately 90 degrees.
HSTIA and ADC MUX diagnostics
We compared the following current ADC MUX paths at 200 kHz, 100 mVpp, RTIA 5 kΩ and PGA ×4:
- HSTIA_P − HSTIA_N
- Current DFT magnitude: 18.8
- Current phase: +23.6°
- Calculated impedance: 32,261.5 Ω
- Calculated phase: −92.0°
- HSTIA_P − AIN1
- Current DFT magnitude: 31.7
- Current phase: +23.9°
- Calculated impedance: 30,435.7 Ω
- Calculated phase: −92.2°
- AIN1 − HSTIA_N
- Current DFT magnitude: 14.4
- Current phase: −135.0°
No ADC MUX combination recovered the expected DUT current signal.
50 kHz versus 200 kHz comparison
We then compared 50 kHz and 200 kHz using identical settings:
- Excitation: 100 mVpp
- HSTIA RTIA: 5 kΩ
- ADC PGA: ×4
- ADC clock: 32 MHz
Results:
50 kHz:
- HSTIA current magnitude: 14.5
- Current phase: +45.0°
- Calculated impedance: 138,303.3 Ω
- Calculated phase: −93.3°
- Calibrated RTIA: 5,639 Ω, −2.1°
- AIN1 − HSTIA_N residual magnitude: 15,239.6
200 kHz:
- HSTIA current magnitude: 30.0
- Current phase: +23.6°
- Calculated impedance: 32,190.4 Ω
- Calculated phase: −91.9°
- Calibrated RTIA: 5,609 Ω, −8.3°
- AIN1 − HSTIA_N residual magnitude: 1.4
The RTIA calibration results appear reasonable at both frequencies, but the DUT current DFT is extremely small. The voltage channel remains responsive.
Our current measurement switch-matrix configuration is:
- D switch: CE0
- P switch: CE0
- N switch: AIN1
- T switch: AIN1 | TRTIA
The current DFT ADC MUX in the standard measurement is:
- ADC positive input: HSTIA_P
- ADC negative input: HSTIA_N
The voltage DFT ADC MUX is:
- ADC positive input: AIN3
- ADC negative input: AIN2
Questions
Could you please advise us on the following?
- Is the above switch-matrix configuration correct for the AD5940 BIOZ evaluation board and Z Test Board in four-wire BIA mode?
- Is HSTIA_P − HSTIA_N the correct ADC MUX configuration for measuring the current DFT?
- Are any changes required to HSTIA bandwidth, CTIA, RTIA, AFE power mode or ADC configuration when increasing the excitation frequency from 50 kHz to 200 kHz?
- Is a 32 MHz ADC clock required or recommended at 200 kHz, or should the standard 16 MHz ADC clock be retained?
- What DFT source and ADC filter settings do you recommend at 200 kHz?
Our current configuration uses:- DFT source: SINC3
- DFT length: 8192
- SINC3 OSR: 2
- High-power AFE mode
- 250 kHz analog bandwidth
- Should the HSTIA RTIA calibration and the measurement sequence use identical power-mode and bandwidth settings?
- Is there a recommended HSTIA RTIA and CTIA combination for measuring approximately 516 Ω at 200 kHz?
- Could the very small current DFT and approximately −90° phase error indicate that we are measuring capacitive feedthrough rather than the actual DUT current?
- Is there an official AD5940 example or verified register configuration for measuring the AD5940 Z Test Board at 200 kHz?
We would appreciate it if you could provide a recommended register configuration or sequence for comparing 50 kHz and 200 kHz measurements using the Z Test Board.
We can also provide the schematic, firmware source, UART diagnostic logs, oscilloscope waveforms and test videos if required.
Best regards,
Sungwoo Electronics