How many AD9082s can be synchronized with a single LTC6953 Clock Buffer?

Question

sanazaim · Accepted Answer

In the current design, we are syncing 2 AD9082’s per LTC6953. This is because we are leveraging the LTC6953 to send reference clocks to the ADF4371S feeding the RX LO conditioning circuit, the ADF4371S feeding the TX LO conditioning circuit, the two ADF4371S’s feeding both AD9082’s, and a reference clock to the FPGA. We are also sending SYSREF signals to the FPGA and both AD9082’s. Depending on your FPGA, you may also require external JTX and JRX core clocks- we are showing both of those generated by the LTC6953 for a total of 10 out of the 11 available outputs. Each subsequent LTC6953 won’t need to provide JTX or JRX core clocks, or FPGA reference clocks which will free extra outputs on the LTC6953. Shown below is a simplified block diagram excluding JTX and JRX core clock signals.

Beyond the scope of this reference design, let’s consider how many AD9082s we can sync with a single LTC6953: If there are 11 buffered outputs, and each AD9082 requires both a SYSREF signal and clock signal, then each LTC6953 could support 4 or even up to 5 AD9082’s.

For more information relating to the LTC6953, here is the link to the product’s landing page: LTC6953 Datasheet and Product Info | Analog Devices

Check out our main wiki page for more information: wiki.analog.com/.../space-based-satcom-ref-design

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How many AD9082s can be synchronized with a single LTC6953 Clock Buffer?