Fundamentals of Clocks

Mar

2017

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Products Mentioned

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ADF4351 Recommended for New Designs
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About the Webinar

Dave Kress Director of Technical Marketing

This webcast will provide an introduction to clocks and frequency synthesis, clock terminology, timing and common applications. We will discuss Phase-locked loops (PLL), Analog PLLs, Digital PLLs and Direct Digital Synthesis.

Webinar Questions

by drewphysics
Webinar

Latest over 8 years ago by UmeshJ
720 1 0
Not Answered
ADS7-V2 and VisualAnalog software and AD9680 ADC board 0
Not Answered

We have the V2 of the ADS7, and an AD9680 ADC board. My first question: 1. the AD9680 requires an input clock of at least 300MHz, correct? We don't have such a clock, but we are pretty sure that the ADS7-V2 could generate it and send it out of the...

ad9680 Fundamentals of Clocks High Speed A/D Converters >10 MSPS Standard High Speed A/D Converters Webinar Forum Show More

720 1 0
by muku_kr
Webinar

Latest over 8 years ago by muku_kr
1705 7 0
Answered
IN AD9833 HOW TO GENERATE 1 KHZ FREQUENCY 0
Answered

HOW TO GENERATE 1 KHZ FREQUENCY INAD9833

Fundamentals of Clocks Webinar Forum

1705 7 0
by BerlinAnalog
Webinar

Started over 8 years ago
444 0 0
Not Answered
AD5933 external clock signal 0
Not Answered

Dear Community, could you help me with my problem, please? https://ez.analog.com/thread/94779 Thank you!

ad5933 calibration clock and timing Fundamentals of Clocks Clocks & Timers source clock Direct Digital Synthesis (DDS) ad5933 i2c ad5933 Webinar Forum Show More

444 0 0
by PKusior

Webinar

Latest over 8 years ago by PKusior
793 1 0
Answered
Could you please talk about the relationship between the phase noise of the reference and that of the in-band, close-loop PLL output? 0
Answered

Could you please talk about the relationship between the phase noise of the reference and that of the in-band, close-loop PLL output?

clocks Fundamentals of Clocks Webinar Forum

793 1 0
by PKusior

Webinar

Latest over 8 years ago by PKusior
697 1 0
Answered
Why do some systems use a frequency doubler instead of a PLL? Do DDS spurs change with phase shift of, for example, 90 degrees versus 0? 0
Answered

Why do some systems use a frequency doubler instead of a PLL? Do DDS spurs change with phase shift of, for example, 90 degrees versus 0?

clocks Fundamentals of Clocks Webinar Forum

697 1 0
by PKusior

Webinar

Latest over 8 years ago by PKusior
629 1 0
Answered
Do you recommend any particular way of filtering DDS DAC output (digital controlled filters?) 0
Answered

Do you recommend any particular way of filtering DDS DAC output (digital controlled filters?)

clocks Fundamentals of Clocks Webinar Forum

629 1 0
by PKusior

Webinar

Latest over 8 years ago by PKusior
529 1 0
Answered
Most of my work is below 1GHz, yet the ADI portfolio seems to almost completely ignore this range. 0
Answered

Most of my work is below 1GHz, yet the ADI portfolio seems to almost completely ignore this range.

clocks Fundamentals of Clocks Webinar Forum

529 1 0
by PKusior

Webinar

Latest over 8 years ago by PKusior
684 1 0
Answered
What device/families are best to produce sine/cosine without conversion to square? 0
Answered

What device/families are best to produce sine/cosine without conversion to square?

Fundamentals of Clocks Webinar Forum

684 1 0
by PKusior

Webinar

Latest over 8 years ago by PKusior
660 1 0
Answered
Is the All-Digital PLL's jitter-cleaning driven by giving a constant time reference (the clock's timing) and therefore detecting where the signal has departed from correct timing? 0
Answered

Is the All-Digital PLL's jitter-cleaning driven by giving a constant time reference (the clock's timing) and therefore detecting where the signal has departed from correct timing?

clocks Fundamentals of Clocks Webinar Forum

660 1 0

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Fundamentals of Clocks

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About the Webinar

Not Answered
ADS7-V2 and VisualAnalog software and AD9680 ADC board 0
Not Answered

Answered
IN AD9833 HOW TO GENERATE 1 KHZ FREQUENCY 0
Answered

Not Answered
AD5933 external clock signal 0
Not Answered

Answered
Could you please talk about the relationship between the phase noise of the reference and that of the in-band, close-loop PLL output? 0
Answered

Answered
Why do some systems use a frequency doubler instead of a PLL? Do DDS spurs change with phase shift of, for example, 90 degrees versus 0? 0
Answered

Answered
Do you recommend any particular way of filtering DDS DAC output (digital controlled filters?) 0
Answered

Answered
Most of my work is below 1GHz, yet the ADI portfolio seems to almost completely ignore this range. 0
Answered

Answered
What device/families are best to produce sine/cosine without conversion to square? 0
Answered

Answered
Is the All-Digital PLL's jitter-cleaning driven by giving a constant time reference (the clock's timing) and therefore detecting where the signal has departed from correct timing? 0
Answered

Fundamentals of Clocks

Products Mentioned

About the Webinar

Not Answered ADS7-V2 and VisualAnalog software and AD9680 ADC board 0 Not Answered

Answered IN AD9833 HOW TO GENERATE 1 KHZ FREQUENCY 0 Answered

Not Answered AD5933 external clock signal 0 Not Answered

Answered Could you please talk about the relationship between the phase noise of the reference and that of the in-band, close-loop PLL output? 0 Answered

Answered Why do some systems use a frequency doubler instead of a PLL? Do DDS spurs change with phase shift of, for example, 90 degrees versus 0? 0 Answered

Answered Do you recommend any particular way of filtering DDS DAC output (digital controlled filters?) 0 Answered

Answered Most of my work is below 1GHz, yet the ADI portfolio seems to almost completely ignore this range. 0 Answered

Answered What device/families are best to produce sine/cosine without conversion to square? 0 Answered

Answered Is the All-Digital PLL's jitter-cleaning driven by giving a constant time reference (the clock's timing) and therefore detecting where the signal has departed from correct timing? 0 Answered

Not Answered
ADS7-V2 and VisualAnalog software and AD9680 ADC board 0
Not Answered

Answered
IN AD9833 HOW TO GENERATE 1 KHZ FREQUENCY 0
Answered

Not Answered
AD5933 external clock signal 0
Not Answered

Answered
Could you please talk about the relationship between the phase noise of the reference and that of the in-band, close-loop PLL output? 0
Answered

Answered
Why do some systems use a frequency doubler instead of a PLL? Do DDS spurs change with phase shift of, for example, 90 degrees versus 0? 0
Answered

Answered
Do you recommend any particular way of filtering DDS DAC output (digital controlled filters?) 0
Answered

Answered
Most of my work is below 1GHz, yet the ADI portfolio seems to almost completely ignore this range. 0
Answered

Answered
What device/families are best to produce sine/cosine without conversion to square? 0
Answered

Answered
Is the All-Digital PLL's jitter-cleaning driven by giving a constant time reference (the clock's timing) and therefore detecting where the signal has departed from correct timing? 0
Answered