Digital Beamforming Techniques for Phased Array Applications

Jan

2017

This webinar has already aired but can still be accessed through the Watch the Webinar button below.

Peter Delos Technical Lead, Aerospace and Defense Applications Group

This webcast is an overview of current challenges and solutions for Digital Beamforming Phased Array applications. The major phased array subsystems will be reviewed and architecture tradeoff options will be discussed.

Electronic Design Services - PartnerZone

Digital Beamforming Techniques for Phased Array Applications

About the Webinar

The use of infrasonic lasers in a 3D retina array of etalon sensors processing both digital and analog information through multiple fiber optics to controllers & SoC 0

AD9238 can't output +1

ADN2820 Reverse bias voltage 0

ADN2820 Question 0

1/25/17 Are any of the solutions mentioned in the presentation available for space applications? 0

1/25/17 How sophisticated can digital beamforming become? 0

1/25/17 How many antenna elements are required to form a beam and how many beams can we form using n*n antenna array... say 28? 0

1/25/17 How can we achieve digital beamforming at high frequency like 28 GHz, when the data is very large? 0

1/25/17 How many RF chains are needed for say N beams? How many users would 1 beam cater to? 0

1/25/17 Can you elaborate the gain phase calibration? 0

1/25/17 Do you have the THA from Hittite in your tool? 0

1/25/17 When a mixer is used with dual band LO plus and LO minus what do I do with the noise figure eq? 0

1/25/17 On slide 9, first point, as operating freq goes up, shouldn't the sentence say "element spacing" goes down... 0

1/25/17 Does analog beam forming have any advantages over digital beam forming? 0

1/25/17 In a typical phased array system, does each of the elements have its own synthesizer? 0

1/25/17 On slide 26 there is no info on phase noise. 0

1/25/17 Direct Sampling: I don't understand what "Gain not distribuited across frequency" means. 0

1/25/17 What's the main challenge for direct sampling so far as Si technology is concerned? Is 28nm/14nm CMOS not good enough? 0