Jeff Keip Jeff Keip Senior Marketing Manager, High Speed DDS Portfolio
Tunc Cenger Product Line Director

Clock jitter attenuators are designed to support the JESD204B serial interface standard for connecting high-speed data converters and field-programmable gate arrays (FPGAs) operating in base station designs. The JESD204B interface was specifically developed to address high-data rate system design needs, ADI's clock jitter attenuators contain the functions that support and enhance the unique capabilities of that interface standard.