Using LTC6655-2.048 in stacked configuration to generate precise 2.048V steps — long-term reliability and accuracy

Hi Otavioc,

Which grade of LTC6655 are you using? Based on the LTC6655C's initial accuracy spec, you can expect up to ~1mV of initial accuracy, either positive or negative. This in itself will already contribute the 1mV error that you are trying to avoid. Can you also clarify the forbidden zone? Are you referring to solder heat shift?

Additionally, errors like long-term drift, temperature coefficient, etc. will root sum square with stacking reference voltages, leading to observing greater errors than you might expect on a single reference. Adding errors are a greater concern for absolute voltage accuracy though, relative step size will still be defined by the individual reference.

The load regulation specs are also important to keep in mind, as stacking the references like this will force each reference to sink/source from above/below. Buffering can help with variable output loads not affecting the entire reference stack.

Comments here are correct. I will add that the operating mode will vary across the devices. For example, the top device will source maximum current from its output, while the bottom device will sink maximum current into its output. These will add load regulation error and drift to their performance. Note that the LTspice model seems to underestimate the quiescent current, it should be higher (to a max of 5mA over temp) into the IN pins.

I have added R5 here to show that not all devices will draw exactly the same quiescent current, this affects the loading across the stack of references. None of this is a problem per se, other than if the max output current exceeds the rated 5mA source/sink, such that the load regulation gets beyond the specification. See the typical performance curves to understand how supply current varies.

1. I'm using LTC6655BHMS8-2.048, which has 0,025% (less than 1mV) initial acuracy. 

2. Forbidden zone was an euphemism. I did some incorrect connections that caused some of the devices to work at higher voltages or output currents than specified. The circuitry is now fixed and as it is shown in the post image, but some devices suffered a slight change in their accuracy. I'm looking for replacing the devices, but I need to know if my circuit can work properly before that.

3. For now I can aford the overall accuracy drift (my hopes are that the random nature of most of this erros cancel each other). As you mention, relative step size will still be defined by the individual reference, and that is what I'm looking for.

4. The load will not be feed directly, there is a buffer stage that sinks a really small current from the references. My concerns are centered in the references sinking and sourcing each other in this serial (can I call it shunt?) configuration and still keeping the accuracy.  

Hi, Bredan. Thaks for the reply!

When I first designed this circuit, I thought that a series configuration would be a good choice to reduce the total current sourced by the top reference by avoiding the need for it to source the quiescent current of all devices individually (n × Iq).
Since the same current flows among the references (Iq), the sinking of one device became the sourcing of the other and the process repeats. Maybe this same quiescent current is the weakness of the circuit, some of them can work properly with the value, while others have its accuracy drifted too far from desired. 

You're welcome! Stacking like this is reasonable conceptually, and should not be a big problem for performance, other than what I'd written. But the details matter. In addition to my earlier reply, it is important to be aware that on startup there is a momentary high-quiescent-current condition as the reference starts up. It is partially illustrated in the current vs. voltage plot, but that is DC, and there is a transient current also. It is critical that this current be available during the startup event.