Temperature sensing transistor configuration

It is recommended to use Q2 as part of a temperature-controlled reference but not necessary. As shown on page 1 of the LTZ1000 datasheet, the use of ADR1000 as a low-noise reference where temperature control is not required is also possible. Temperature coefficient in this case is not specified.

Hello,
Thank you for your reply.
However, my post asked a different question.
Using Q2 as the temperature sensor, is there any reason not to use Q2 configured as a diode, with collector connected to base?  The question arises since the example application in the data sheet uses Q2  with a constant base emitter voltage, with collector current as a temperature measurement.

Thanks for clarifying! My concern here would be how the circuit might interact with Q2 configuration due to on-chip parasitics. We have only characterized the configuration shown in the datasheet. The circuit is carefully balanced and not designed for flexibility.

The following paper documents ADR1000 performance with two significant differences from the configuration given by ADR1000 data sheet figure 9.  

https://www.mdpi.com/2673-8244/4/1/7

Can you comment on error contributions that might be caused by these differences?

First, Q2 is configured as a diode.

Second, this application locates the heater as a cathode load of the pass transistor, rather than as an emitter load per the data sheet.  Assuming several volts across the heater in thermal steady state, this increases leakage from the heater, but may make it more constant over external temperature variation.

Data sheet figure 1 shows two diodes between the heater and the internal node that includes the zener anode and the base of temperature compensating transistor Q1.  Configured according to data sheet Figure 9, pin 1 of the internal heater will be several volts above the aforementioned internal node, diode leakage will contribute reverse biased leakage current into that node.   Configured with pin 1 at V+ and pin 2 connected to the collector of the pass transistor, per the cited article, both of the aforementioned reverse biased diodes contribute reverse bias leakage current, but the current may vary less over ambient temperature variation.

Thank you,
M.Reich

Summarizing, 

Does connecting Q2 as a diode increase parasitic current from its base?

Do the normally reverse biased diodes shown in figure 1 of the ADR1000 data sheet represent the on-chip parasitics?  

I'm afraid I don't have much comment on this configuration as I don't have experience with it. I don't see a serious problem with running Q2 diode-connected, but it will also depend on the implementation. Q2 base current would not increase as long as it is not in saturation. Note that I*R drops anywhere in the Zener path create part of the tempco, so any different partitioning of currents can have an effect on TC. The parasitic heater diodes you refer to are only shown as a way to help designers understand that certain nodes must have a specific bias relative to other nodes; for example Pin1 > Pin2. Actual heater bias voltage should not have an effect as long as it does not forward bias the diode. The heater is designed to work over a range of conditions.

Thank you for your reply.

The LTSpice model does seem to include a plausible model for the parasitic diodes. 

Can one rely on the LPSpice model for a reasonable approximation of the parastic diodes with normnal reverse bias?

Thank you,

M.Reich

I think the diode models will be more conceptual. They will do what is needed in the case of forward bias to flag a problem. I don't believe that they are accurate in reverse-bias, and such current is swamped by Dz current and heater current. The LTspice model was not designed to be ppm-level accurate, it is only for design functionality.

Thank you for explaining the limitations of the LTSpice model.

I used it mainly for optimizing a design based on the article cited above at 27 Feb 1:56PM.  The ADR1000 block includes what appears to be a  realistic thermal model, so for example, at ambient TEMP = 25C, and a temperature regulation setpoint of 70C, the die reaches the set point at about 99 seconds simulated time.  At 120s, the reference output becomes stable to within no more than several uV.  

Does the model realistically represent reference voltage vs temperature at the recommended operating current? 
Can you say that thermal resistance the model assumes for either die to ambient or case to ambient?

Thank you,
M.Reich

Hi, the model was designed to give an understanding of what to expect with regards to startup as you have seen. It is not super-accurate; it just gives some behavioral information. We don't model variation and cannot anticipate the thermal environment in an arbitrary application. The purpose of the model is to help get the circuit running and show general behavior. It is not going to be very helpful in optimizing to ppm or usec.

Thank you

Thank you