Design advice for using ADR3650 to power a bridge sensor load cell data acquisition system and act as an ADC/DAC voltage reference...

Hi, hope I can help here.

1. ADR3650 is fully released and can be used at any desired volume. 

2. It is recommended to use the Eval board as a guide for design and layout with ADR3650. Information can be found on the product landing page on ADI's website. UG-2079 (Rev. 0) There is information in the datasheet regarding the use of Vout Sense and GND sense to avoid errors caused by IR drops on the PCB. You will want to use these to connect the bridge and converters appropriately.

3. Unlike most LDOs, ADR3650 is designed to be stable sourcing, sinking, and with no output current. Therefore it is more sensitive to output capacitance. Using a Vout plane will create a variety of capacitances to all kinds of nodes in the circuit. It would be better to use traces for Vout force and sense. The sense removes the need to have a plane (or pour) for Vout.

4. ADR3650 can certainly handle this. The Cout sensitivity needs to be considered, but the load should not be an issue. The ADC and DAC would need to work with Vref=Vsupply for this to work.

Best regards,

Brendan

Hi Brendan,

Thanks for the quick and complete response - much appreciated!  Using this chip should make my design considerably simpler than what I've been exploring with shunt references, op-amp buffers, separate LDO, etc.  Yes, the ADC and DAC both support Vref=Vsupply so I should be all set on that end.  Would you or someone at ADI be available to do a sanity check on the layout I come up with, or should I just post a layout snippet on this thread?

Thanks!

-Dino

Hi Dino,

I'm happy to help! You can post the layout here or go through Central Apps via the website. Support | Analog Devices

Best regards,

Brendan

Hi Brendan,

Great, thanks!  I should have something to look at in the next day or so...

-Dino

Hi Brendan,

Below are some screenshots of the layout I've come up with so far for my design based on the ADR3650.  Some background on my thinking for the design:

1. Left side (i.e. left of the vertical cut shown in screen 2) is all the analog circuitry and it includes: U7(ADR3650); U5(AD8557); U8(ADC); U6(DAC).  All are powered by and referenced to the 5.0VA traces shown in screen 3 below from the ADR3650.  The ADR3650 is powered by the 5.5VD input which generated by an LDO elsewhere on the board.
   1. My core analog signal is from a bridge-based load cell (2mV/V up to 20mV/V output) that comes in on the four pins in the lower left/center of the board (pin1 is EXC, pin2 is GND, pin3 is IN+, pin4 is IN-).  The load cell is excited by the 5.0VA from the ADR3650.  The differential inputs are connected to a differential RC low pass filter on the input side (right side) of the AD8557.  The output from the AD8557 goes to the ADC and DAC for data acquisition and system control.
2. Screen 1 (Top layer, signals, RED)
3. Screen 2 (Inner layer 1 (below top layer), Ground plane, GREEN) shows the star pattern I'm using to isolate the grounds for the analog circuitry from the rest of the grounds on the board.  In essence, the ground plane has vertical cuts that create a small pathway (or "star") for connecting the analog and non-analog sections of the board.
   1. Digital traces (e.g. SPI, I2C, etc.) are routed over this pathway.
   2. All component ground pads are connected to the ground plane with vias immediately adjacent to the component (e.g. bypass caps, etc.).
4. Screen 3 (Inner layer 2 (below inner layer 1), power plane, BROWN) shows all the power trace routing.
5. Screen 4 (Bottom layer, signals, BLUE).  Shows auxiliary signal traces that couldn't be routed on the top layer.
6. My thinking was to use copper pours with many vias around the VOUT_SENSE/FORCE (ADR3650 pins 6,7) and GND_SENSE/FORCE (ADR3650 pins 3,4) to minimize any parasitic effects for the ADR3650...

I would very much appreciate your thoughts on the design and what things I should consider for improvements, especially regarding the ADR3650 and its FORCE/SENSE pins.

Thanks,

-Dino

Hi Dino,

You will want to think about the current paths with respect to the Force/Sense. You want currents to flow in the Force connection, and measurements to be made with respect to the sense connections. You do not want to connect force and sense at the voltage reference. Instead, connect them at the bridge, and star them with the ADC connections also at the bridge. Run separate connections to the supplies, because the IR drop is not an issue there.

Hi Brendan,

Thanks for your feedback.  I'll have a think on it and come up with something along the lines you've described.  Just to be clear when you say "bridge" you mean the load cell correct?  If yes, then does using the load cell connector pins as the "star points" make sense?  Other than this issue, does everything else make good sense on the layout?

Thanks,

-Dino