LTC6655 layout

Let me discuss the layout.

Q1 There is a description on page 15(datasheet)"Power and ground planes should be omitted under the voltage reference IC for best stability."

  Is there any effect on temperature hysteris depending on the presence or absence of ground planes?

Q2 Could you give me the board information that measured the temperature hysteris in the table specification item?

  • +1
    •  Analog Employees 
    on May 28, 2020 5:32 AM

    Hi Yuji,

    A1    Yes. The reason why omitting the power/ground planes below the area of the IC is because of the mechanical stress cause by it when temperature changes. Different material have different Coefficient of Thermal Expansion. The material of the PCB has its own CTE, the same goes for the copper, with this the IC will be subjected to multiple mechanical stress due to multiple CTE of different materials. But this has a little effect on the performance of the IC. The main contributor for the Mechanical Stress are the metal lead and the package. For sample layout on this case please see link

    A2.    You can use the link provided above for temperature hysteresis test. I'm still following up on what the actual layout of the board is, I'll get back on you on this. You can also refer on this for more information about tab cut of the board.