I have found that of all the modes we have ever tried to put throughthe part this mode has the shortest HSync and it is being ignored by the AD7441A. If I increase the sync width by about +10% at the source the ADV7441A then gets it. Is there some sort of Sync noise filter that I can tweak the threshold on?
The SPPD block is preceded with a deglitch filter that removes Hsync and Vsync pulses narrower than 7 clock periods of the external crystal oscillator. Thus with an external crystal oscillator of 28.63636 MHz frequency, pulses narrower than 0.27us will be filtered out by the deglitch filter. This is the behavior you are observing.
It is possible to bypass the deglitch filter so that the DUT can correctly process video inputs that have narrow Hsync pulses with the settings outlined below. Note that the deglitch filter control value cannot read back as is located in the write-only function register 0xB5 of the User Map.
Disabling the deglitch filter Set User Map, Reg 0xB5 to 0x8 (Check in our Analog devices Software Manual for corresponding bit in your DUT)
Unfortunately on the ADV7403 it is not possible to bypass this filter. The bypass option was first added on the next generation ADV7441Asince).