Analog.com Analog Dialogue Wiki English 简体中文
EngineerZone
EngineerZone
  • Log In
  • Site
  • Search
  • User
  • Support

    Popular Forums

    • RF and Microwave
    • Power Management
    • Video
    • FPGA Reference Designs
    • Precision ADCs
    • Linux Software Drivers
    • SigmaDSP Processors & SigmaStudio Dev. Tool

    Product Forums

    • A2B
    • Amplifiers
    • Analog Microcontrollers
    • Clock and Timing
    • Data Converters
    • Direct Digital Synthesis (DDS)
    • Energy Monitoring and Metering
    • Interface and Isolation
    • MEMS Inertial Sensors
    • Processors and DSP
    • Switches/Multiplexers
    • Temperature Sensors
    • Voltage References
    View All

    Application Forums

    • Audio
    • Automated Test Equipment (ATE)
    • Condition-Based Monitoring
    • Depth, Perception & Ranging Technologies
    • Embedded Vision Sensing Library
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Precision Technology Signal Chains Library
    • Video
    • Wireless Sensor Networks Reference Library

    Design Center Forums

    • ACE Evaluation Software
    • ADEF System Platforms
    • Design Tools and Calculators
    • FPGA Reference Designs
    • Linux Software Drivers
    • Microcontroller no-OS Drivers
    • Reference Designs
    • Signal Chain Power (SCP)
    • Software Interface Tools
    • System Demonstration Platform (SDP) Support
  • Learn

    Highlighted Webinar

    Multidimensional Simulations of Beamformers and other RF Integrated Circuits in Keysight SystemVue

    Recent Discussions

    • ADALM-PLUTO maximum frequency
    • Issue running built programs on Pluto
    • Activity: Simple Op Amps, For ADALM1000 Fig. 1.3 Buffering example
    • ADALM-PLUTO [NETWORK] vs [USB_ETHERNET]
    • Using buffer size different from 2**n

    Places

    • ADI Education Home
    • ADI Education China
    • ADI Education India
    • ADI Education Philippines
    • StudentZone (Analog Dialogue)
    • Virtual Classroom

    Latest Webinars

    • Multidimensional Simulations of Beamformers and other RF Integrated Circuits in Keysight SystemVue
    • Improve Smart Building Energy Efficiency with Industrial Ethernet Controlled Air Conditioning (HVAC) Systems
    • Sustainable Motion Control Solutions for High Performance Servo Drives
    • Audio Design Solutions for Augmented and Virtual Reality (AR/VR) Glasses
    • Robust Industrial Motor Encoder Signal Chain Solutions
    View All Webinars
  • Community Hub

    Challenge Yourself!

      KCC's Quizzes: AQQ 236 about strange marking on airplane engines
    View All

    Places

    • Community Help
    • Logic Lounge

    Resources

    • EZ Code of Conduct
    • Getting Started Guide
    • ADI: Words Matter
    • Community Help Videos
    View All
  • Blogs

    Highlighted Blogs

    Can LTspice Break Physics?

     

    Crawl, Walk, And Run - The Journey To Create The Phaser

    Latest Blogs

    • Hardware Holds The Key To Making Industrial Systems IEC 62443 Compliant
    • Behind the Scenes of DIYRadio Blogs: An Introduction
    • Empowering Surveillance Cameras To Capture A Scene Without Being Heard
    • Mastering The Metrics Makes Specifying Encoders Simpler
    • Understanding Secret Key Cryptography Without Formulas
    Read All Blogs

    ADI Blogs

    • EZ Spotlight
    • The Engineering Mind
  • Partners

    Electronic Design Services - PartnerZone

    • Boston Engineering
    • Calian, Advanced Technologies
    • Colorado Engineering Inc. (DBA CAES AT&E)
    • Clockworks Signal Processing
    • Epiq Solutions
    • Fidus
    • PalmSens
    • Richardson RFPD
    • Tri-Star Design, Inc.
    • VadaTech
    • Vanteon
    • X-Microwave
    View All
Video
Video
Documents Why does the ADV7842 HS output jitter by 1 pixel clock period when the output pixel clock is 157.5MHz?
  • Q&A
  • File Uploads
  • Docs/ FAQs
  • Members
  • Tags
  • More
  • Cancel
  • FREE RUN
  • +AD724: FAQ
  • +AD725: FAQ
  • +AD7441A: FAQ
  • +AD8122: FAQ
  • +AD8380: FAQ
  • +AD8381: FAQ
  • +AD9388A: FAQ
  • +AD9389: FAQ
  • +AD9880: FAQ
  • +AD9882: FAQ
  • +AD9884A: FAQ
  • +AD9888: FAQ
  • +AD9889B: FAQ
  • +AD9978: FAQ
  • +AD9981: FAQ
  • +AD9984A: FAQ
  • +AD9985A: FAQ
  • +AD9994: FAQ
  • +ADA4891: FAQ
  • +ADDI7004: FAQ
  • +ADI Video Parts: FAQ
  • +ADV202: FAQ
  • +ADV212: FAQ
  • +ADV3002: FAQ
  • +ADV3224/25/28/29: FAQ
  • +ADV7123: FAQ
  • +ADV7125: FAQ
  • +ADV7128: FAQ
  • +ADV7171: FAQ
  • +ADV7174: FAQ
  • +ADV7179: FAQ
  • +ADV7180: FAQ
  • +ADV7180W: FAQ
  • +ADV7181C: FAQ
  • +ADV7181D: FAQ
  • +ADV7182: FAQ
  • +ADV7183B: FAQ
  • +ADV7184: FAQ
  • +ADV7185: FAQ
  • +ADV7188: FAQ
  • +ADV7202: FAQ
  • +ADV7280: FAQ
  • +ADV7281: FAQ
  • +ADV7282: FAQ
  • +ADV7283: FAQ
  • +ADV728x: FAQ
  • +ADV7341: FAQ
  • +ADV7343: FAQ
  • +ADV734X: FAQ
  • +ADV7390: FAQ
  • +ADV7393: FAQ
  • +ADV739x: FAQ
  • +ADV7401: FAQ
  • +ADV7403: FAQ
  • +ADV7441A: FAQ
  • +ADV7480: FAQ
  • +ADV7481: FAQ
  • +ADV7482: FAQ
  • +ADV749x: FAQ
  • +ADV7510: FAQ
  • +ADV7511: FAQ
  • +ADV7513: FAQ
  • +ADV7520: FAQ
  • +ADV7604: FAQ
  • +ADV7610: FAQ
  • +ADV7611: FAQ
  • +ADV7612: FAQ
  • +ADV7613: FAQ
  • +ADV7614: FAQ
  • +ADV7619: FAQ
  • +ADV7622: FAQ
  • +ADV7623: FAQ
  • +ADV7625: FAQ
  • +ADV7626: FAQ
  • +ADV7627: FAQ
  • +ADV7630: FAQ
  • +ADV7800: FAQ
  • +ADV7802: FAQ
  • -ADV7842: FAQ
    • ADV7842 3D Capabilities
    • ADV7842 Design Support Files
    • ADV7842 evaluation board schematic download
    • ADV7842 5V tolerant pins - Hot Swap and CEC
    • Advantiv EVAL-ADV7842-7511 Video Evaluation Board
    • Customer hardware validation scripts for ADV7842
    • How can I get the absolute position of DE on an active line with ADV7842?
    • How do I calculate manual gain settings in the ADV7844 and ADV7842?
    • I2C write sequence
    • The Audio FAQ for ADV7842 and ADV7604
    • Why does the ADV7842 HS output jitter by 1 pixel clock period when the output pixel clock is 157.5MHz?
  • +ADV7844: FAQ
  • +ADV7850: FAQ
  • +ADV78xx: FAQ
  • +adv8003: FAQ
  • +ADV8005: FAQ
  • +Advantiv: FAQ
  • +AN-1191: FAQ
  • +analog input muxing: FAQ
  • +Apple TV: FAQ
  • +Customer hardware validation scripts: FAQ
  • +CVBS: FAQ
  • +Decoder Product: FAQ
  • +DVP Evaluation Software: FAQ
  • +EVAL-MELODY: FAQ
  • +HDCP-Enabled Parts: FAQ
  • +HDMI: FAQ
  • +I2C: FAQ
  • +PCB Trace Impedance Calculator: FAQ
  • +VESA Standards: FAQ
  • +xtal Load Caps: FAQ

Why does the ADV7842 HS output jitter by 1 pixel clock period when the output pixel clock is 157.5MHz?

For analogue graphic inputs and where the pixel output clock is expected to be in the range of 156.5MHz and 158.5MHz; the following I2C writes are required for the ADV7842 and for the ADV7844.

DPLL Map, Register 0xA0 = 0Ah. If this register write is not done, the horizontal sync may vary by plus or minus 1 pixel clock period.

This register must be returned to it's default value of 00h for all other video formats. 

  • hs
  • clock.h-sync
  • adv7844
  • jitter
  • kick
  • adv7842
  • output
  • 157.5mhz
  • clock
  • sync
  • horizontal
  • 157mhz
  • Share
  • History
  • More
  • Cancel
Related
Recommended
Social
Quick Links
  • About ADI
  • ADI Signals+
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Incubators
Languages
  • English
  • 简体中文
  • 日本語
Newsletter

Interested in the latest news and articles about ADI products, design tools, training and events? Subscribe today!

Sign Up
Analog Logo
©1995 - 2023 Analog Devices, Inc. All Rights Reserved
沪ICP备09046653号-1
  • Sitemap
  • Legal
  • Privacy & Security
  • Privacy Settings
EngineerZone Uses cookies to ensure you get the best experience in our community. For more information on cookies, please read our Privacy & Security Statement.