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Why does the ADV7842 HS output jitter by 1 pixel clock period when the output pixel clock is 157.5MHz?

For analogue graphic inputs and where the pixel output clock is expected to be in the range of 156.5MHz and 158.5MHz; the following I2C writes are required for the ADV7842 and for the ADV7844.

DPLL Map, Register 0xA0 = 0Ah. If this register write is not done, the horizontal sync may vary by plus or minus 1 pixel clock period.

This register must be returned to it's default value of 00h for all other video formats.