In reset and powerdown modes the ADV7182's output pins (P0:P7, Hs, VS/FIELD/SFL and LLC) are tristated.
Just confirmation, that sounds no internal pull up/down resisters in ADV7182,
and back end video processor need to ignore output pins information during reset and powerdown state?
In reset and powerdown modes the digital output pins are tristated (i.e. high impedance / open circuit).
No data is output when the ADV7182 is in reset and powerdown mode.
Therefore there should be no data on the output pins for a backend processor to ignore when the ADV7182 is in reset and powerdown mode.
However after the part is programmed out of powerdown mode it may take it a period of time to re-lock to an analog video source. Until the ADV7182 has fully locked to a video source it may output incorrect data. I advise that the backend processor ignore the data from the ADV7182 until the ADV7182 has fully locked to the video source (IN_LOCK and FSC_LOCK bits are high).
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Senior Applications Engineer,
Analog Devices Inc.