The following FAQ applies to the ADV7182, ADV7280, ADV7281, ADV7282, and ADV7283 models of video decoders.
Setting the TOD bit (User Map, Register 0x03, bit[6]) to 1 will trisate the pixel bus outputs ( P0:P7) and the synchronisation pins (HS and VS/Field/SFL).
Note that that a separate control TRI_LLC (User Map, Register 0x1D, bit[7]) is needed to tristate the LLC pin. Setting TRI_LLC to 1 will trisate the LLC pin.
Note that the synchronisation pins (HS and VS/Field/SFL) are only available in the ADV7182 and ADV7280 models. It is also possible to force the HS and VS/Field/SFL pins to be active even when the TOD bit is set. Setting the TIM_OE bit (User Map, register 0x04, bit [3]) to 1 will force the HS and VS/Field/SFL pins to be active.
For example if the TOD bit is set to 1 and if the TIM_OE bit to 1 will result in the pixel bus outputs ( P0:P7) being tristated and the synchronisation pins (HS and VS/Field/SFL) being active.