When ctm is trying to do DMA transfer to FPGA, the load of firmwire to circuit
is going ok, no problem but f.e.
DREG signal is staying up even though it should go down.
Do you have new application note for ADV212 ? What is the main difference in
to old revision ?
The ADV202 and ADV212 are functionally the same, except that the ADV212 has an
additional JTAG interface for boundary scan description language (BSDL).
The ADV212 requires up to 50% less power than the ADV202.
The ADV202 and the ADV212 have the same footprint and pin-out.
There are 2 modes of operation
• In DREQ/DACK DMA mode, DREQ/ is asserted as soon as sufficient data is
present to fulfill the DMA burst or DMA single access settings in the EDMOD
register. An assertion of DREQ/ should be answered from the host processor by
an assertion of DACK/ and either RD/ or WE/.
• In DCS encode mode, DREQ/ is asserted when the number of words in the FIFO is
greater than or equal to the threshold value for that FIFO. In DCS decode mode,
DREQ/ is asserted when the number of word spaces in the FIFO is greater than or
equal to the threshold for that FIFO. Data accesses require the DACK/ pin to be
asserted with RD/ or WE/.