control) are coming from a Xilinx FPGA.
There will be a short time, while the FPGA is configuring, where the inputs to
the ADV7125 will be floating.
Do you have any recommendations for the ADV7125 in this regard?
The digital inputs to the ADV7125 should not be left floating - if they are
left floating they will be opened to surrounding noise which can make the pins
high or low. The digital inputs should be connected via resistors from the FPGA
to the ADV7125.
The control pin SYNC should be connected to ground via a zero ohm resistor. The
control pin BLANK should be connected high via a zero ohm resistor.
Since the output of the FPGA is either going to be at logic 0 or logic 1, then
the digital inputs to the ADV7125 should be connected via resistors and not
tied to ground. The o/p clock should be connected to the ADV7125 clock input.