Maybe the Temporal Decimation (TDE, bit 1 on Subaddress 0E) cannot be disabled
in this mode.
In LLC Mode FIELD is working as expected.
Bit 3 of (hidden) register 2B hex must be set to logic high. For normal LLC
mode operation, this bit must be set to logic low(the default). This bit makes
the f bit in SAV/EAV behave correctly, that is it goes either high or low
depending on whether an odd or even field of video is being decoded. The field
pin also behaves correctly.