ADV7625 HDCP Authentication  without a 5V signal

ADV7625/26/27 HDMI Receiver Authentication without 5V signal

►Attempting to authenticate (ADV7625/26/27 Rx) when no 5V signal is present causes the HDCP key controller to get stuck

• HDCP cipher will not calculate R0’ (R0’ remains at all zeros)

►Once this occurs, HDCP key controller must be reset

• Main I2C reset (IO Map, 0xFF[7]
• Power-on reset

Workaround and Detection

►Workaround

• Isolate the ADV762x from the HDCP activity on the DDC bus until a stable 5V signal is detected
• Initialise HDMI Rx Repeater Map 0x7B[0] to 1
• When cable_det_x_raw
• When cable_det_x_rawfor the active port, set HDMI Rx Repeater Map 0x7B[0] to 1

►Detection

• To detect this, the following algorithm is suggested
• Use AKSV_UPDATE_RX1 / AKSV_UPDATE_RX2 and HDMI_ENCRPT_RX1 / HDMI_ENCRPT_RX2 interrupts to detect if the lock state has occurred
• In normal operation both the AKSV_UPDATE and HDMI_ENCRPT interrupts trigger when authentication is successfully completed
• If 3 x AKSV_UPDATE interrupts occur without a corresponding HDMI ENCRPT interrupt, this suggests the HDCP Key Controller needs to be reset

Code changes for the workaround

►Code changes

• Whenever there is a no TMDS, the DDC port is disabled to avoid the HDCP controller lock state.
• When we receive the XREP_EVENT_RX_TMDS_DETECTED in app_notify.cADIAPI_RxHdmiEnDdc() needs to be called to handle the DDC port.

►app_notify.c

►rx_hdmi.c

• Include the below API for enable/disable the DDC.

                  ATV_ERR ADIAPI_RxHdmiEnDdc(BOOL Enable)

                  {

                     #if((RX_DEVICE ==7625)||(RX_DEVICE ==7626)||(RX_DEVICE ==7627))  

      return(HAL_RxHdmiEnDdc(Enable));

#else

      return (ATVERR_NOT_AVAILABLE);

#endif

         }

►rx_6g_hal.c

• Include the below HAL API for enable/disable the DDC.

ATV_ERR HAL_RxHdmiEnDdc(BOOL Enable)

{

    if(!Enable)

    {

        HAL_I2CWriteByte(VRX_REPEATER_MAP_ADDR, 0x7b, 0x01);  

    }

    else

    {

        HAL_I2CWriteByte(VRX_REPEATER_MAP_ADDR, 0x7b, 0x00);  

    }

    return (ATVERR_OK);

}

►7625_ini_hal.c , 7626_ini_hal.c & 7627_ini_hal.c

• HAL_RxInitHAL_RxHdmiEnDdc(FALSE);