I2C require two bus line – SDA and SCLMost I2C devices can communicate at 100 kHz or 400 kHz.
Start/Stop Condition:Start and Stop condition are always generated by the master.Each I2C command initiated by master device starts with a START condition and ends with a STOP condition. For both conditions SCL has to be high. A high to low transition of SDA is considered as START and a low to high transition as STOP.
Generally our i2c driver perform the following sequence: Start condition – write operation (sub-address)-start condition- Read operation (data)-stop condition. Need to send STOP bit when the whole process reading is done. To terminate a read/write sequence a stop signal must be sent.
Please make sure with below Read/Write sequences, a.Write Sequence 1) Send the start condition 2) Send the slave address 3) Check for the acknowledge 4) Send the sub-address to be written to 5) Check for the acknowledge from 6) Send the data to write to specified sub address 7) Check for the acknowledge 8) If No-acknowledge send the stop condition 9) Send a stop condition
b. Read Sequence1) Send the start condition2) Send the slave address3) check for the acknowledge4) Send the sub-address to be read from5) check for the acknowledge6) Send the start condition7) Send the slave address8) check for the acknowledge9) If No-acknowledge send the stop condition10) If acknowledged read the data from specified sub-address12) Send a No-Acknowledge13) Send a stop condition
Here we can find the more details about i2c bus specification and also timing related details I2C Bus Specification and User Manual
Note: Some i2c drivers work with 7 bit addressing, if your software/tool is using 7-bit i2c address, In that case, we need to right shift the 8 bit map address to one.For example: 0x98 IO Map – 8 bit address 0x98>>1 =0x4C – 7 bit addressPlease crosscheck: 0x98 is an 8-bit I2C address. In other words, it assumes the software/tool is using 8-bit I2C addresses.In-case if your software/tool is using 7-bit I2C addresses (fairly common), you should use 0x4C instead.
NACK(No ACK): I2C reset is the only write that will no ACK back. The reset bit resets the I2c engine before it has a chance to ACK back.The I2C master controller will receive a no acknowledge condition on the ninth clock cycle when chip Reset is implemented.