Q&A - Recent Threads

Equalizer settings for 4K30Hz

kaihatsuk — Thu, 06 Aug 2026 08:28:48 GMT

The equalizer frequency is set via register 0x8A of the HDMI Rx Main Map.

The maximum frequency is 240 MHz, but what is the optimal value for 4K30Hz?

Does the optimal value depend on factors such as HDMI cable length and signal quality, rather than the TMDS clock frequency?

SXGA 1280X1024 , @50Hz

Obk93 — Wed, 05 Aug 2026 14:10:07 GMT

Hi,

Does the ADV7403BSTZ-110 support SXGA 1280X1024 , @50Hz ?

Thanks,

Omer

ADV7511 Sync Output Polarity Control

aimPoint — Tue, 04 Aug 2026 10:58:55 GMT

Hi all,

I am having some confusion regarding the sync signal output polarity control of the ADV7511 and would appreciate your help.

For my application using the ADV7511, I need to invert the polarity of the output sync signals.

However, in the ADV7511 Programming User Guide Rev. G, page 157, Register 0x17, the descriptions for Bit[6] Vsync Polarity and Bit[5] Hsync Polarity appear inconsistent when Sync Adjustment Register (0x41[1]) = 0 (Case 2).

I found the following two different descriptions:

0 = sync polarity pass through
1 = sync polarity invert

and

0 = High polarity
1 = Low polarity

This has caused some confusion.

(1)

For Case 2 (0x41[1] = 0), do you think the following description is a typo?

0 = High polarity
1 = Low polarity

(2)

My current settings are:

0x17[6:5] = 2'b00
0x41[1] = 0

With these settings, the behavior is as follows:

Negative-polarity VSYNC input → Negative-polarity VSYNC output
Negative-polarity HSYNC input → Negative-polarity HSYNC output

If I change the settings to:

0x17[6:5] = 2'b11
0x41[1] = 0

will the behavior become:

Negative-polarity VSYNC input → Positive-polarity VSYNC output
Negative-polarity HSYNC input → Positive-polarity HSYNC output

Could you please confirm whether this understanding is correct?

Thank you in advance for your support.

Best regards,

aimPoint

Input Capacitance of ADV7403

Obk93 — Mon, 03 Aug 2026 11:08:10 GMT

Hello,

I added an ADV7403 component to my design, and in order to understand the bandwidth of the analog signal that I am feeding into the analog inputs of the ADV7403, I am trying to determine the input capacitance of those pins so I can include it in my simulation..this is not mentioned in the datasheet.

Thanks.

MAX96717F ctrl1_vc_map + MAX96724: configuration required for serializer-remapped VC streams; UG Table 10/example contradiction

Jassy — Thu, 30 Jul 2026 13:44:30 GMT

Product: MAX96717F serializer + MAX96724 quad deserializer
Mode: GMSL2 pixel mode, 3Gbps link, RAW12 1920x1536@30
Input sensor VC: VC0
Target serializer-side remap: VC2 or VC3

Goal
----
Assign distinct standard virtual channels to two identical cameras at the MAX96717F serializer, allowing the MAX96724 to use identity pass-through.

Documentation discrepancy
-------------------------
The public MAX96717/F/R User Guide contains conflicting register definitions:

Table 10 states:
- 0x0330 bit7 = Ctrl1_vcx_en
- 0x0331 bit5 = Ctrl1_vc_map_en

The following "Extended Virtual Channels Programming Example" instead writes:
- 0x0331 <- 0xB0 for VC extension
- 0x0330 <- 0x20 for VC remapping
- 0x0345 <- 0x50 for VC0 -> VC5

On our MAX96717F device, 0x0330 bit7 does not retain a written 1 and always reads back as 0. The bit locations used by the programming example do accept and retain the written values:
- 0x0331 <- 0xB0
- 0x0330 <- 0x20
- 0x0345 <- 0x30 or 0x20

Please confirm the correct register and bit definitions for MAX96717F and whether Table 10 or the programming example is authoritative.

Observed downstream behavior
----------------------------
Before the serializer writes, the MAX96724 passes the stream using MAP entries matching source VC0.

After applying the programming-example register locations, the previous source-VC0 MAP configuration no longer produces output, while the MAX96724 video pipe continues to report VIDEO_LOCK. This shows that downstream matching behavior changes, but we have not independently decoded the resulting on-wire VC.

We tested the following MAX96724-side combinations:
- controller 1 csi2_vcx_en enabled: 0x094A = 0xD0
- controller 1 csi2_vcx_en disabled: 0x094A = 0xC0
- MAP entries matching the intended new standard VC (VC2 or VC3), with identity SRC/DST mappings for RAW12, FS and FE
- MAP entries matching the original VC0 as a control
- extended-VC MSB registers for the relevant pipe left at zero because the intended VC is <= 3

All tested combinations produced zero frames at the MIPI output.

Questions
---------
1. What exact MAX96724 configuration is required to receive a pixel-mode GMSL2 stream remapped by MAX96717F ctrl1_vc_map?
2. When the remap target is a standard VC <= 3, is ctrl1_vcx_en required on the serializer or deserializer?
3. Does enabling ctrl1_vcx_en change the GMSL2 link encoding even for a target VC <= 3?
4. Is there any per-link or per-pipe extended-VC unpack/enable setting on MAX96724 not described in the public User Guide?
5. Please confirm and correct the MAX96717/F/R User Guide discrepancy between Table 10 and the programming example.

We can provide the exact write/readback sequence and full MAX96717F/MAX96724 register dumps if required.

FTP Issues - Could not connect to server

rpster — Mon, 27 Jul 2026 21:18:33 GMT

I am trying to access the FTP server as instructed by the eval kit, but I keep getting "could not connect to server". I have tried setting it to insecure FTP, on other machines both PC and Mac, and with other FTP clients. Note that the server cannot be contacted, so the username/password is irrelevant. Is there an alternative non-FTP download location?

Blimp software download error

Christopher542 — Thu, 23 Jul 2026 17:52:26 GMT

I want download Blimp software tool to program OSD for ADV8005 but EngineerZone link is broken. Please someone attach Blimp software tool.

Getting output negative need to know reason

smartwaves — Thu, 23 Jul 2026 11:10:15 GMT

byte <= x"17"when total_count = "0000001" else --1
x"02"when total_count = "0000010" else --2

x"56"when total_count = "0000011" else --3
x"00"when total_count = "0000100" else --4
x"1C"when total_count = "0000101" else --5

x"56"when total_count = "0000110" else --6
x"01"when total_count = "0000111" else --7
--x"40"when total_count = "0001000" else --8
x"00"when total_count = "0001000" else --8

x"56"when total_count = "0001001" else --9
x"80"when total_count = "0001010" else --10
x"11"when total_count = "0001011" else --11

x"56"when total_count = "0001100" else --12
x"82"when total_count = "0001101" else --13
--x"C3"when total_count = "0001110" else --14
x"D3"when total_count = "0001110" else --14
--87 00
x"56"when total_count = "0001111" else --15
x"88"when total_count = "0010000" else --16
x"10"when total_count = "0010001" else --17 --10
--
x"56"when total_count = "0010010" else --18
x"8A"when total_count = "0010011" else --19
x"0C"when total_count = "0010100" else --20

x"56"when total_count = "0010101" else --21
x"84"when total_count = "0010110" else --22
x"08"when total_count = "0010111" else --23

x"56"when total_count = "0011000" else --24
x"8C"when total_count = "0011001" else --25
x"CB"when total_count = "0011010" else --26

x"56"when total_count = "0011011" else --27
x"8D"when total_count = "0011100" else --28
x"8A"when total_count = "0011101" else --29

x"56"when total_count = "0011110" else --30
x"8E"when total_count = "0011111" else --31
x"09"when total_count = "0100000" else --32

x"56"when total_count = "0100001" else --33
x"8F"when total_count = "0100010" else --34
x"2A"when total_count = "0100011" else --35

x"56"when total_count = "0100100" else --36
x"87"when total_count = "0100101" else --37
x"A0"when total_count = "0100110" else --38

x"56"when total_count = "0100111" else --39
x"86"when total_count = "0101000" else --40
x"80"when total_count = "0101001" else --41

x"56"when total_count = "0101010" else --42
x"33"when total_count = "0101011" else --43
x"04"when total_count = "0101100" else --44 04 this is the register settings 10bit EAV/SAV BT 656 as input

ADV7403 Grounding

Obk93 — Wed, 15 Jul 2026 14:35:11 GMT

Hello,

I am designing a relatively simple board based on the ADV7403. The board receives analog RGB video from another board and outputs digital video to an FPGA.

I have read the grounding recommendations in the ADV7403 datasheet and hardware manual.

Due to my board layout considerations, I would like to ask whether it is acceptable to use one continuous, solid ground plane without any split or slot at all.

I will still keep a clear physical separation between the analog and digital sections:

The analog RGB inputs and associated circuitry will be placed in the analog area.
The FPGA and the digital pixel bus will be placed in the digital area.

This is a simple board whose main components are only the ADV7403 and an FPGA. There are no other high-speed digital interfaces on the board.

Would you consider this grounding approach to be appropriate for this application?

Thank you,

Omer

Cannot output YCbCr 4:2:2 10-bit at 4K@30Hz.

kaihatsuk — Wed, 15 Jul 2026 06:22:29 GMT

Outputting YCbCr 4:2:2 10-bit at 1080p 60Hz works fine.

However, at 4K 30Hz with YCbCr 4:2:2 10-bit, the display does not show an image; instead, a free-run signal is output.

It should be supported under the HDMI 1.4 standard—does the ADV7626 not support this?

ADV7611 Setup script help

Astronuat21 — Tue, 14 Jul 2026 19:27:36 GMT

Are there any examplary setup scripts available for specific output formats for the ADV7611? Specifically, Im looking to output in 24-Bit SDR 4:4:4 Mode to drive my RGB screens, which is one of the modes in the data sheet (Rev. E) I did take a look at the reference file "ADV7611-VER.3.0c.txt" but I am not very knowledgeable in I2C so if anyone can help it would be much appreciated. The screens I am using are only 800x480 and 480x272 so I do not need anything for high resolutions

HDMI Çıkış Alamama ve ı2c hatası

emirhann — Mon, 13 Jul 2026 12:08:14 GMT

Hello, I have an ADV7181CEBZ, and I'm trying to get an HDMI output from the CVBS input. But I can't get it to work.

Configuration of ADV7403 for Stanag class B as input and 20 bit YUV422 as output

Rashmika — Thu, 09 Jul 2026 09:32:23 GMT

Hi ADI,

Can you provide the procedure to configure the ADV7403 for stanag 3350 class B as input and 20-bit YUV422 as output?

Thank you in advance,

With regards
Rashmika

ADV7127 Settling time issue and internal refrence

Steven1980 — Mon, 06 Jul 2026 17:07:31 GMT

Working on a design with the ADV7127 and running into some odd behavior. The outupt of the DAC is terminated into a 78.7 ohm resistor to get the output range we are looking for. This is a none video application. The data is being clocked at 20MHz. When the output is stepped form 0x000 to 0x3FF we get an overshoot to the correct voltage and then the output drops to ~70% of expected then ramps to expected voltage in ~100us. I have used an older version of the ADV7127 in a similar application and did not see this type of issue. In that case it was the ADV7127KR50.

Questions:

1) The datasheet is very unclear on the internal refrence. The ADV7127KRUZ140 has an internal refrence, correct?

2) What could be causing the odd behaviour? the voltage rails all look clean and decoupling is performed per the datasheet.

Question Regarding SPI Tunneling between MAX96717F and MAX96716F

mateo — Thu, 25 Jun 2026 14:38:23 GMT

I am writing to ask for your advice regarding SPI tunneling between a MAX96716F deserializer and a MAX96717F serializer.

Hardware Setup

The current hardware setup is:

NVIDIA Jetson Orin Nano running a custom Linux image (analogdevicesinc/gmsl: Gigabit Multimedia Serial Link (GMSL) technology from Analog Devices, Inc. (ADI)).
AD-GMSL522-SL carrier board.
MAX96716F EV kit connected to the carrier board through the Samtec connector. (i2c address 0x98)
MAX96717F EV kit connected to the MAX96716F over GMSL Link A using a coaxial cable. (i2c address 0x80)
An SPI peripheral connected to the serializer side.

Software

The Jetson device tree and pinmux have been modified to enable the SPI interface and pins on the carrier board. The SPI controller is successfully claimed by the Linux kernel, and communication through /dev/spidev has been verified.

Repository:

Intended SPI Configuration

The intended SPI direction is:

Jetson Orin Nano: SPI Master
MAX96716F: SPI Subordinate
MAX96717F: SPI Main
SPI peripheral: SPI Slave

Current Observations

Using simple SPI loop scripts, I first transmitted a single byte repeatedly (one byte per packet) and later repeated the tests using four-byte transfers.

On the deserializer side, the SPI interface behaves as expected:

SS1 asserts correctly.
The SPI clock is generated correctly.
MOSI contains the expected transmitted data (e.g. 0xA5).
The SPI waveform on the deserializer MFP pins appears correct.

However, the serializer side does not produce a valid SPI interface.

Specifically:

The serializer SPI clock output remains at a constant logic level.
The serializer SS1 output also remains at a constant logic level.
The serializer MOSI pin exhibits some activity, but it does not appear to be a valid SPI MOSI waveform.

During the one-byte transfer test I occasionally observed a waveform on the serializer MOSI pin that resembles the transmitted data, but it is significantly compressed in time and is not accompanied by a corresponding SPI clock or slave-select signal so it might be something completely different.

During the four-byte transfer test, the serializer MOSI pin still exhibits unusual activity. It appears somewhat noisy and is only present during portions of the deserializer SPI clock activity. The serializer SPI clock and SS1 outputs remain inactive.

Because of this, it appears that some form of signal or control activity is reaching the serializer, but the serializer does not begin driving a valid local SPI interface.

Register Observations (using GMSL SerDes Gui v6.9.4)

The SPI byte counter on the deserializer increases during transmission, for example:

RIB 98 0177 1 1

RIB 98 0177 1 2

RIB 98 0177 1 3

RIB 98 0177 1 ...

while the corresponding serializer SPI byte counter remains at zero:

RIB 80 0177 1 0

The packet counters (0x0025) increase on both the deserializer and serializer, which suggests that packets are traversing the GMSL link.

Configurations Tested

So far I have tested:

SPI Mode 0 and SPI Mode 3.
One-byte and four-byte SPI transfers.
Different SPI Main/Subordinate configurations.
Different GPIO/MFP configurations.
RO/BNE configurations from the MAX96717F user guide (max96717fr-user-guide.pdf).
Verification of SPI timing using an oscilloscope.
Verification that the Jetson SPI controller is functioning correctly.

At this point, the remaining issue appears to be that the serializer does not generate the expected local SPI outputs despite the deserializer correctly receiving SPI traffic.

I was wondering whether there are any additional registers, initialization steps, or prerequisites specific to the MAX96716F/MAX96717F SPI control channel that might explain this behaviour.

In particular:

Is there any additional configuration required before the serializer begins driving its local SPI interface?
Are there any required link-initialization or reset procedures specific to the MAX96716F/MAX96717F? It seems to Auto-Link when both evkits are detected (indicated by LOCK LEDs on each evkit)
Are there any recommended registers or status indicators that you would suggest checking to verify that the SPI control tunnel is operating correctly?

I have attached oscilloscope and SerDes GUI screenshots, register dumps, and photographs of the setup for reference.

Any suggestions or guidance would be greatly appreciated.

Thank you all

ez.analog.com/.../spi-register-dump.txt ez.analog.com/.../general-register-dump.txt

ADV7280A NRND Status

Phil.A — Mon, 22 Jun 2026 17:15:34 GMT

We use about 300 to 400 (ADV7280AWBCPZ) of these a year and were looking at using the ADV7280A-M version but noticed these are not recommended for new designs (NRND). Is there going to be a replacement for these at some point and when will there be a notice for last time buy for these?

SDRAM for ADV7842

kshigemori281 — Fri, 19 Jun 2026 03:22:34 GMT

Hi,

The SDRAM we have been using has reached EoL. As a result, we are currently searching for an alternative SDRAM to use with the ADV7842.

Could you please confirm whether the following IC can be used in combination with the ADV7842?

Best regards

DSI (DPHY v1.4) to HDMI2.0 bridge IC

jagen — Tue, 16 Jun 2026 13:13:34 GMT

Hi,

We have not been able to identify a suitable DSI-to-HDMI 2.0 bridge IC for our application. Kindly suggest a recommended solution that aligns with our system requirements.

Please refer to the high-level block diagram below for better understanding of the system,

Regards,

Jagen M

How to convert image format RGB (4:4:4) to YCbCr(4:2:2) with ADV7611?

EKTAI — Tue, 16 Jun 2026 05:55:28 GMT

Hi,

Input image format: HDMI-RGB(4:4:4)

Output image format: YCbCr (4:2:2)

How to convert image format RGB (4:4:4) to YCbCr(4:2:2) with ADV7611?

Could you share ADV7611 register configuration ?

Thanks.

Alternate Part

Vigneshwari — Wed, 10 Jun 2026 10:14:28 GMT

Hi,

We are using the ADV7125 For RGB-VGA Conversion in our Existing Design. However ,the device is now mentioned as NRND (Not Recommended for New Design) in ADI site.

Could you please suggest any suitable alternative part for the ADV7125 ?

Preferably, We are looking for Resolution - 1024 (W) x 768 (H) Max.

And also,Please suggest alternate part for ADV7393.

Thanks in advance,

G.Vigneshwari

ADV7181D eval software

julian_hiorns — Wed, 10 Jun 2026 09:58:42 GMT

Can anyone tell me how to download the register setting software for the ADV7181D? I've found the page, but the app itself is not available.

ADV7613 Custom resolution set

ADV7613Eng — Wed, 10 Jun 2026 03:59:08 GMT

Hi,

I am designing a video bridge board using the ADV7613 to interface a PC (HDMI Source) directly to a custom embedded WUXGA LCD panel (Dual-Link 24-bit VESA LVDS display).

Here are my physical panel and timing specifications from the LCD datasheet:

Active Resolution: 1920 x 1200 @ 60Hz
Pixel Clock (PCLK): 147.0 MHz
Horizontal Timing: H-Active = 1920, H-FP = 24, H-PW = 2, H-BACK = 24 (Total Line Width = 1970)
Vertical Timing: V-Active = 1200, V-FP = 20, V-PW = 2, V-BACK = 18 (Total Frame Height = 1240)
Output Interface: Dual-Link LVDS (8 data lanes total), VESA Mapping format.

Regards

Jeevan

Custom resolution set

ADV7613Eng — Mon, 08 Jun 2026 12:24:56 GMT

Hi,

I am designing a video bridge board using the ADV7613 to interface a PC (HDMI Source) directly to a custom embedded WUXGA LCD panel (Dual-Link 24-bit VESA LVDS display).

Here are my physical panel and timing specifications from the LCD datasheet:

Active Resolution: 1920 x 1200 @ 60Hz
Pixel Clock (PCLK): 147.0 MHz
Horizontal Timing: H-Active = 1920, H-FP = 24, H-PW = 2, H-BACK = 24 (Total Line Width = 1970)
Vertical Timing: V-Active = 1200, V-FP = 20, V-PW = 2, V-BACK = 18 (Total Frame Height = 1240)
Output Interface: Dual-Link LVDS (8 data lanes total), VESA Mapping format.

Regards

Jeevan

ADV7842: Excess noise when capturing component video

superchromat — Sat, 06 Jun 2026 02:39:28 GMT

We have a design that incorporates an ADV7842 as a 12 bit per channel analog to digital converter for HD component video. When we supply an HD video signal at 1080p24 (pixel clock 74.25MHz) we see excessive broadband noise in the captured image data at ~12 LSB (12 bit). This is twice the level of noise that we've measured from a commercial device that also happens to use an ADV7842 in the same experimental setup.

The ADV7842 feeds its data over 36bit per pixel parallel single clock / single edge to another chip on the board from Macro Image Technologies (MIT), that outputs a TMDS stream which is captured by a BlackMagic Design UltraStudio as HDMI. We have verified that if I generate a test pattern within the MIT chip, the data captured by the UltraStudio is bit perfect. Likewise, I have verified that a test pattern generated internally by the ADV7842 shows no noise.

We have tested this with a variety of analog sources generating a 50% gray full frame field as Y/Pb/Pr with sync on Y. The Y signal has a tri-level sync pulse extending 300mV below and above blanking level. The video is 0-700mV above blanking. The peak to peak of sync + video is 1V. For the grey test image, Pb and Pr at at 0V (AC coupled) and Y is active at 350mV.

In the current measurement setup, the DAC is showing <900 uV RMS noise on each of those channels during the active video region.

The video signal goes into the ADC using the datasheet suggested divider network of 24R series, 51R shunt, AC coupled via 100nF. This is a 0.68x divider and provides the 75R termination to match the source impedance.

The ADV7842 is has clamping enabled, and configured for a 300mV sync tip for AGC. Capturing at 12bits for the range of 0-1V (sync tip clamp level referenced), the least significant bit is 244uV (1V / 2^12). With source noise at 900uV, it is scaled down by the divider to 0.68x, with 612uV of RMS noise reaching the AIN pin of the ADC. So, we would expect to see 2.5 LSB of noise.

Note, this assumes that the ADC is noiseless. Given that no noise figure is published, we'll go with that assumption - particularly given that we have another device from another manufacturer that uses an ADV7842, and it exhibits 2x less measured noise than my device. This implies that the noise is my fault, not that of the ADV7842 intrinsically. I have tested two of my boards, and they both show the same excess noise.

The ADV7842 is configured with Automatic Gain Control (AGC) enabled with sync tip tracking. Reading back CP_AGC_GAIN returns 0x30F or 1.53x. So the digital gain stage should take the 2.5 LSB of noise and multiply it up to 3.8 LSB. However, we are measuring over 3x that at 12 LSB.

Here is a zoomed in section of a capture of the 50% grey field (unsure how well this will survive compression, but you should see the random noise):

We have the MIT chip set up to output 12bit YUV 4:4:4 TMDS, as the UltraStudio is only capable of capturing 10bit 4:2:2. While it can capture RGB 12bit, the source into the ADV7842 is Y/Pb/Pr, so we want the channels in the captures to match the channels being input into the ADC. Loading a captured YUV lossless TIFF file into R to analyze the noise, we see the following output:

The main things to note is the width of the histograms compared to the source, with RMS readings of 2.9mV versus the ~900uV measured RMS noise from the source. The noise spectrum is flat for Y, with the expected rolloff seen for Pb/Pr given that this is a 4:2:2 capture.

This capture was taken with the internal anti-aliasing filter _disabled_ on the ADV7842. If we set the AA filter to a cutoff of 10MHz, the noise spectrum remains basically the same (with the addition of some spurs that don't meaningfully contribute to the overall RMS noise):

This suggests that the noise is coming from after the AA stage, and thus is not a reflection of noise present at the Analog In pins of the ADV7842.

The ADV7842 has separate low noise LDO's powering PVDD and AVDD. The noise measured on those lines is low, with less than 1uV noise in the 0-37MHz band. Furthermore, injecting orders of magnitude more broadband noise directly into PVDD or AVDD does not change the measured noise spectra. VDD and CVDD are supplied by the boards general 1V8 digital supply, and while that supply is noisy (16mV broadband AC RMS), again, injecting further noise into those rails does not change the measured noise spectrum of the ADC output. The board is a 6 layer board with a continuous power plane for 1V8 and continuous single ground planes. Decoupling for PVDD and AVDD is directly under the BGA on the back of the board. REFP/N are decoupled as per the datasheet, close to their pins.

So, in short, we am seeing 12LSB of broadband noise that doesn't reflect the noise in our sources. The noise is not impacted by AA filter settings and is not wholly explained by the 1.5x AGC digital gain. Nor can we see a source of the noise on the rails supplying the ADV7842.

We have included a full dump of the registers below.

What should I be looking at next?

ez.analog.com/.../ADV7842_5F00_register_5F00_dump.txt

ADV7182A 576i stream not being recieved by monitor/tv at the output of an ADV7511 (within a Zedboard)

ArnauVB64 — Sun, 31 May 2026 23:03:22 GMT

Hi everyone,

I developed a board using the ADV7182A which correctly outputs a blue screen when in free run mode and no input (576i/50hz 4:2:2 itu-r bt 656-4 compliant with embedded syncs @ 27MHz) as shown in the picture below. Have tried to configure the ADV7511 to take this input from its pins 19:12 (HD11 to HD4 in the zedboard) and send it right through to several monitors/TVs but none seem to work.

I assume that since my system has a 27MHz clk and the pixel clock is 13.5MHZ, the ADV7511 automatically repeats pixels in order to match the minimum frequency for TMDS. Have tried configuring it in several ways and either VHDL or C code in the PS sent through the FPGA fabric. None have seemed to work, despite trying multiple configurations for it. Here is the latest iteration of the VHDL configuration (each Hex value is in the format [Address][Value]):

-- Fixed Registers That Must Be Set (Table 14)
-----------------------------------------------
x"9803", x"9AE0", x"9C30", x"9D61", x"A2A4", x"A3A4", x"E0D0",
x"F900",

-----------------
-- Main Power Up & Sync Adj
-----------------
x"4112",

---------------------------------------
-- Input mode
---------------------------------------
x"1514", -- Input ID: 4
x"16B4", -- Output Format
x"1765", -- VSync and HSync, 4:2:2 to 4:4:4 Up Conversion
x"4810",

---------------------------------------
-- Sync extraction
---------------------------------------

x"3003", x"3103", x"32F0", x"3308",x"3403",
x"3520", x"36D6", x"3705", x"38A0",x"3912",x"3A00",
x"D703", x"D803", x"D9F0", x"DA08",x"DB03",

---------------
-- Output mode
---------------
x"AF06" -- HDMI mode

ADV7182A Output captured by an oscilloscope as a parallel clocked signal (the Cb Y Cr Y sequence matches with the default configuration):

Would gladly appreciate any insight into which part of the configuration for the ADV 7511 might be the culprit or if my assumptions about the double pixel clock are incorrect. Hope the information provided is sufficient.

Thanks in advance!

Arnau