Q&A - Recent Threads

Can ADV7511K send data without HS/VS (DE mode only)?

kjpetlig — Thu, 16 Apr 2026 19:54:04 GMT

I would like to use ADV7511K for non-video purposes (just sending 24 bit data), can this part accept data without HS/VS? Typically this is called "DE mode"

ADV7403BSTZ-110 RS-170 Video Detection Issue

NileshCore — Thu, 16 Apr 2026 06:57:32 GMT

I am currently using the ADV7403BSTZ-110 in a design where I am feeding a monochrome RS-170 video signal (640*480). However, the IC is detecting this as an NTSC signal (720*480), which results in a black border and incorrect framing on the output.

Since the ADV7403 datasheet does not explicitly list RS-170 support, I have the following questions

Is there a specific register configuration or script for the ADV7403 that allows it to correctly frame a RS-170 input without defaulting to 720-pixel NTSC width?
If the ADV7403 cannot support this, could you recommend a similar video decoder IC (with similar pinouts or specifications) that fully supports NTSC, PAL, and monochrome RS-170?

I have attached my current schematic ( i am giving RS170 input to the pin no 76 of IC ) and a sample of the video output for your reference. Any guidance or scripts you can provide would be greatly appreciated.

CVBS input video disturbance issue

jianzhou — Wed, 15 Apr 2026 10:35:47 GMT

Dear Engineer,

To avoid the jitter issue caused by the ADV7280 I2P function, I disabled the I2P function and used the downstream RV1126B to perform de-interlacing. Now I find that with CVBS input, there is a disturbance phenomenon, while S-video input shows no disturbance. I also verified with the internal test pattern using REG0x14's FREE_RUN_PAT_SEL(100% color bars/Luma ramp/Boundary box), and there was no disturbance. How can I optimize the disturbance issue specifically for CVBS input?

Settings for the equaliser gain on the RX side (zctrl and gctrl)

ADV7625SDAPullupResistor — Wed, 15 Apr 2026 04:38:06 GMT

Please tell me how to adjust the equaliser gain on the RX side of the adv7626, and which register to use.

ADV7511 ARC only - How to connect TMDS pins?

t1msu100 — Sat, 11 Apr 2026 01:54:54 GMT

Hello,

I'm interested in using the ADV7511 only for it's ARC functionality.

The RGB->HDMI video conversion part will be unused.

The HW-Guide suggests that the RGB input pins should be tied to ground.

What should done with the 8 TMDS pins?

Can they be left unconnected on both the IC and the HDMI connector for easier routing or should they be connected the same as if I was using the video part?

Best regards

ADV7401 PCB TRACE length matching

Esakkidurai — Tue, 07 Apr 2026 10:08:30 GMT

Dear Team,

Good day to you all !! We are using the ADV7401BSTZ-110 video decoder in our design.

The input signal is Graphics RGBs and the output format is 24-bit pixel data.

Q1) Could you please share the allowable PCB trace length mismatch (allowable Skew) requirements for analog RGB signlas?

Q2) What is the allowable PCB trace length mismatch (allowable Skew) among the pixel data lines RGB[0:23],control lines and LLC clock for ADV7401 chipset?

Thanks & Regards,

Esakki.

[ADV7480] Reset timing during battery brown-out and DVDDIO absolute maximum concern

HTCV3 — Fri, 03 Apr 2026 04:32:09 GMT

Hi,

We have a question regarding the ADV7480 reset behavior during an abnormal battery condition in customer system.

In customer application, when a momentary battery brown-out occurs, the ADV7480 is powered down and the RESETL pin is driven low. However, we have observed that the RESETL output transitions to low approximately 4 ms later than the DVDDIO power-off.

As a result, during this short period, the voltage level on the RESETL pin exceeds the DVDDIO rail and temporarily violates the absolute maximum rating of DVDDIO + 0.3 V.

Our questions are as follows:

1. Is this condition acceptable from a device reliability standpoint, considering that the duration is very short (approximately 4 ms) and the event occurs only during abnormal power conditions?
2. Is there a known risk of device damage or long-term reliability degradation due to this short-duration exposure beyond the absolute maximum rating?
3. Does Analog Devices have any recommended mitigation techniques (for example, series resistance on RESETL or other minimal circuit measures) to reduce the risk without requiring major circuit changes such as level shifters?

Please note that implementing major circuit modifications would have a significant impact on customer design, so we would appreciate your guidance on whether this behavior can be reasonably tolerated or how it can be mitigated with minimal impact.

We apologize for the short notice, but we would appreciate a response by April 6th.

Best regards,

ADV7604 non document register

gabi.furman — Tue, 31 Mar 2026 11:23:10 GMT

On my GPU board I am using the ADV7604 to capture RGBHV video input at XGA resolution.

The device work properly but I get a background analog noise on the image.

During debug I mistakenly write AFE MAP register 0x12 with value 0x00 and it solve the problem.

When looking into the SW register list , I cannot find that such register exists .

appreciate your support.

ADV7280A: Unstable chroma on first active line of BT.656 (STANAG Class C / NTSC)

jon510 — Mon, 30 Mar 2026 14:24:03 GMT

Hello,

I am using the ADV7280A with a STANAG 3350 Class C (NTSC RS-170A timing equivalent) composite input and 8-bit embedded BT.656-4 output.

Symptom:
The first active row of one field shows blinking colored dots (unstable chroma) on saturated colors such as SMPTE bars. Luma appears stable. Row 1 and the following rows are clean.

Isolation:
We checked the raw BT.656 output directly with an FPGA Integrated Logic Analyzer (ILA). The ADV7280A outputs 487 active lines, and the chroma variation is already present on the first active line of the raw byte stream before our FPGA crops it to 720x486 lines for the downstream modules.

Attempted fixes:
We tested several documented registers and EngineerZone-recommended initialization sequences, including 0x27, 0x2B to 0x2E, 0x3D, 0x38 to 0x39, and 0xEB to 0xEC, without any change to the first-line behavior. We have also checked with different video sources.

For reference, our baseline ADV7280A configuration is:
0x00 = 0x00
0x02 = 0x14
0x03 = 0x0C
0x04 = 0xBD
0x1D = 0x64
0x0F = 0x00
0x3A = 0x07

Questions:

1. Is this a known ADV7280A behavior for STANAG Class C / non-broadcast NTSC sources, specifically on the first active line of a field?

2. Could this be related to NTSC field-boundary / SCH burst phase behavior, or to how the ADV7280A handles chroma decoding / comb filtering on the first active line?

3. Is there any documented or undocumented register sequence that can improve first-line chroma stability, or is the recommended approach simply to mask this line downstream?

Thanks in advance for the support.

Kind regards,
Jonathan

ADV7391WBCPZ – Device-to-Device Variation in Large-Signal Transient Response (Right-Side Trailing Artifact)

sakelover — Tue, 24 Mar 2026 01:29:14 GMT

Dear ADI FAE Team,

We are currently evaluating the ADV7391WBCPZ in an NTSC composite video application and have encountered a device-dependent artifact related to large-signal transitions.

When the digital input experiences a full-scale step change (e.g., luminance transition from 0 to 255), a visible trailing artifact appears toward the right side of the displayed image. From a signal integrity standpoint, this resembles a large-signal transient response issue, potentially associated with reconstruction filter behavior, DAC slew limitations, output stage settling characteristics, or edge-enhancement / sharpness processing interaction.

Importantly, this phenomenon is not consistent across all devices. Under identical FPGA video timing, register configuration, PCB layout, load conditions, and power supply environment, only a subset of ADV7391 devices exhibit this right-direction trailing behavior. This suggests a possible device-to-device variation in analog transient performance, internal filter stability margin, or output driver dynamics.

For your reference, the current register configuration programmed via I²C from the FPGA is listed below:

0x17 : 0x02 (Software reset)

0x00 : 0x1C (All DACs enabled)

0x01 : 0x00 (SD mode)

0x02 : 0x20 (Default)

0x80 : 0x10 (NTSC standard selection)

0x82 : 0xCB

We would greatly appreciate your technical guidance on the following points:

1. Are there any known silicon variations or characterization notes related to large-amplitude step response, DAC settling behavior, or composite output reconstruction filtering in ADV7391 devices?

2. Are there recommended register settings to mitigate overshoot, ringing, or right-side trailing artifacts (e.g., sharpness control, adaptive filtering gain, output drive strength, or internal LPF configuration)?

3. Could this behavior be influenced by output load impedance sensitivity, AC-coupling network design, or PCB parasitics affecting loop stability?

4. Is there any application note or internal technical documentation addressing transient artifacts under full-scale video transitions?

Thank you very much for your support.

Best regards,

Behavior of ADV7610 and I2C pins during a continuous reset state

KKZ — Thu, 19 Mar 2026 09:39:21 GMT

Hi,

Q1: Is there any issue with the ADV7610 device if the RESET pin is held low to maintain a continuous reset state while the following conditions are met?
- All power supplies (TVDD, VDDIO, CVDD, PVDD, DVDD) are applied.
- 5V is applied to the RXA_5V pin.
- A clock signal is input to the XTALP pin.
- There is no TMDS input, and the TMDS bus is in a high-impedance state.

Q2: What is the state of the SCL and SDA pins when the RESET pin is held low (continuous reset state)? There are some ICs sharing the same I2C bus (SCL, SDA), and we are planning to perform I2C communication with those ICs while the ADV7610 is held in reset.

Best regards,

MSL level for ADV7535BCBZ-RL7

MSY — Thu, 19 Mar 2026 06:59:24 GMT

Hi Team,

Please help to share the MSL level of ADV7535BCBZ-RL7 on priority.

Power rails design and current consumption

Roey — Thu, 12 Mar 2026 06:59:01 GMT

Hi Team

I am going to use the ADV7391 in my design. My setup is:

Video output: SD (NTSC/PAL)

Mode of operation: x8 over sampling, Low drive current mode

Output Driver: ADA4807 Gain of x2 and with 75ohm serial resistor

IO Voltage: 1.8V

My questions are:

1. What is the full current consumption from VAA at low current mode? The datasheet specifies 50mA but that is in Full drive mode.

2. I saw that VAA range is from 2.6V to 3.45 why the range is so large?

3. I would like to provide the best power for the component. What is your recommendation for achieving that?

a. If you suggest using LDO, can you suggest a low dropout LDO because i want to use my 3.3V voltage as input voltage of the LDO

b. I saw that datasheet suggests ferrite beads as filters. Many discussions claim that ferrite bead may add noise due to its inductance and resonance with the capacitor. What do you think of that?

c. Can i use single LDO to feed same power sources such as PVDD, VDD and VDD_IO?

Thanks in advance

Regards,

Roey

Video Test Pattern Generator IP issues

Chercheur — Thu, 12 Mar 2026 05:03:43 GMT

I've started working on video tracking implementation on FPGA. The research paper I am following uses Zynq UltraScale + ZCU104 evaluation board. Initially I am trying to run HDMI in/out exdes on vivado which includes a video test pattern generator which is a built-in vivado IP generated through HLS. But it is giving error

[Synth 8-439] module 'exdes_v_tpg_0_v_tpg' not found ["d:/MS_Notes/ResearchPRoject/MOSSE101/v_hdmi_rx_ss_0_ex/v_hdmi_rx_ss_0_ex.srcs/sources_1/bd/exdes/ip/exdes_v_tpg_0/synth/exdes_v_tpg_0.v":196] , though location is correct and file is present over there.

Best Regards

ADV7125 - Internal reference no longer supported?

Bobrze — Tue, 10 Mar 2026 12:13:05 GMT

Hello,

I have noticed that the current version of datasheet omits description of the internal voltage reference in ADV7125. Older datasheet mentions either internal, or external Vref can be used. Current datasheet only directs you the Vref pin must be connected with external voltage reference.

Is that a mistake in the new datasheet (info got somehow missing) or does it mean, that ADV7125 now always requires an external reference? How to distinguish the chip version then please?

Thank you for your expertize.

Regards,

Jan

Chuyển đổi DVI sang LVDS

MIKOTRAN22 — Mon, 09 Mar 2026 02:46:22 GMT

Hi,

Our customer would like to use following configuration. Can ADV7842 configurate it?

Input : DVI/HDMI

Output : RGB / 24bit

If ADV7842 can as above, how to set the registers? I'd like to know that script.

When I confirmed "ADV7842-VER.5.9c.txt", I could not find the configuration.

Or please tell me which register to change from which section setting in order to make the setting.

ADV7842-7511 Evaluation Board EEPROM

MIKOTRAN22 — Thu, 05 Mar 2026 06:57:37 GMT

I’m currently designing a board using the ADV7842. On the ADV7842-7511 Evaluation Board, I see both SPI EEPROM and I²C EEPROM.

How can I program and write firmware/data into these EEPROMs?

Video differential line drivers

satya — Tue, 03 Mar 2026 04:20:29 GMT

Hi,

I'm looking for video buffers (PAL to PAL), audio buffers(driving for long distance and load) and video format converter(PAL to RGB and NTSC to PAL).

please suggest me the suitable IC.

satya

Noise occurs at sampling frequencies of 176.4 kHz and 192 kHz.

SHIGETO — Tue, 03 Mar 2026 00:18:27 GMT

As shown in the diagram, I built a circuit combining the ADV7511 and ADV7619.

The audio format between the ADV7619 and the ADV7511 is SPDIF.

When the sampling frequency is set to 176.4 kHz or 192 kHz, the audio output from the ADV7511 becomes noisy. At that time, the N and CTS values are incorrect.

・192 kHz (Normal)
N = 24576
CTS = 148500

・192 kHz (Noise from ADV7511 output)
N = 6144
CTS = 37124

What should I check?

Best regards.

ADV7611 with TP2915

Hareesh9415 — Mon, 02 Mar 2026 10:33:29 GMT

We are using the ADV7611 together with the Techpoint TP2915 to convert an HDMI input to an AHD/TVI output. When configuring the ADV7611 using the script below, I noticed the following issues:

HDMI MAP (0x6A[4], tmds_clk_a_raw) → reading 0x00
IO MAP (0x6F[0]) → reading 0x01

I am setting the resolution to 1080p60 using the following register configuration:

98 FF 80   # I2C reset
98 FD 44   # CP
98 00 1E   # VID_STD = 1080P60 @ 60Hz
98 01 05   # Prim_Mode = 101b HDMI-COMP
98 03 42   # 36-bit SDR 4:4:4 Mode 0
98 05 28   # AV Codes Off
98 0B 44   # Power up part
98 0C 42   # Power up part
98 14 7F   # Max Drive Strength
98 15 80   # Disable Tristate
98 19 83   # LLC DLL phase
98 33 40   # LLC DLL enable

44 BA 01   # Set HDMI FreeRun
44 BF 17   # Force FreeRun; Manual color settings
44 C0 00   # Manual color: Green
44 C1 00   # Manual color: Red
44 C2 A0   # Manual color: Blue
44 C9 05   # Disable auto buffering of FreeRun parameters

The LLC clock is correctly running at 148.50 MHz, and I can see activity on the ADV7611 output bus. However, the video is not displayed on the TP2915 output.

What could be the reason for this issue?

ADV7480 Current Consumption During Reset States

shimizu-yasu — Mon, 02 Mar 2026 09:10:53 GMT

Hello.
We have received the following question from our customer.

During a hardware reset of the ADV7480 (RESET pin asserted Low) and during a software reset (I2C/SPI register-based reset), what is the typical current consumption?
Is it the same as the values listed under “POWER-DOWN CURRENTS” on page 6 of the datasheet, or are there any differences?

Best regards.

ADV7341/ADV7393 use case

Sree1729 — Mon, 02 Mar 2026 07:58:36 GMT

Hi,

I am planning to use ADV7611 and ADV7393 to convert HDMI to CVBS.

While checking the evaluation board of ADV7611 I came across ADV7341 used on the eval-board to put out CVBS.

1. Why ADV7341 is not recommended for new design?

2. Are ADV7341 and ADV7393 similar in functionality? I am asking this to see if I can validate the ADV7611 and ADV7393 combination.

MIPI clock can not output

yyl123hf — Mon, 02 Mar 2026 03:45:02 GMT

While reading the MAX96712 registers, I confirmed that video_lock and pipe_lock are both set. However, after enabling CSI_OUT (0x40B-bit2), the SOC side does not receive any bus data. Using an oscilloscope to probe the CSI bus, I observed waveforms on D0 ~ D3, but the CLK bus remains constantly low. I attempted to set force_csi_out_en (0x8A0-bit7), but the result remains the same. Reading registers 0x8D0~0x8D3 shows that the data is continuously toggling.

The waveforms for D0：

CLK are shown below：

Do you have any troubleshooting suggestions for this issue?

[ADV7480] About CP_OUT_MODE[1:0] setting

HTCV3 — Wed, 25 Feb 2026 11:22:46 GMT

Hi,

The customer is using RGB888 when outputting MIPI-CSI.

Checking the ADI recommended script, the following settings are found:
(Ex.)01-29 HDMI to MIPI TxA CSI 4-Lane - RGB888, Up to 600Mbps:
　　IO-MAP(0xE0) 0x04=0x02: RGB_OUT=1
　　IO-MAP(0xE0) 0x12=0xF0: CP_OUT_MODE[1:0]=00

Could you please explain in detail the difference between the settings CP_OUT_MODE[1:0]=00 (SDR 444) and CP_OUT_MODE[1:0]=01 (SDR 422 2ch)?
Is any conversion or processing performed internally within the ADV7480?

Best regards.

Chipset Suggestion for RGsB+PAL to MIPI-CSI2 conversion

GaneshTamilselvam — Tue, 24 Feb 2026 09:41:54 GMT

Hi Team,

We are looking for chipsets to convert 2x RGsB + PAL video signals to MIPI-CSI2 to interface with processor.

Have attached block diagram below for your kind reference.