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Recently I write a I2C driver in Verilog module to configure ADV7181B.These following signals are captured in logic analysis.

There is a question:in the blue rectangle area,every time when accessing the IC's address or register,the ACK signal trigger low by the slave.

We see the ACK appears low in 3/4 of a complete period of SCLK and high in the left time of SCLK,can this be correct?Because when FPGA is waiting ACK the master releases the "LINK"(direction signal control a tri-inout in FPGA),I wonder if ACK is always logic low in a whole period of SCLK?