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Recently I write a I2C driver in Verilog module to configure ADV7181B.These following signals are captured in logic analysis.

There is a question:in the blue rectangle area,every time when accessing the IC's address or register,the ACK signal trigger low by the slave.

We see the ACK appears low in 3/4 of a complete period of SCLK and high in the left time of SCLK,can this be correct?Because when FPGA is waiting ACK the master releases the "LINK"(direction signal control a tri-inout in FPGA),I wonder if ACK is always logic low in a whole period of SCLK?

  • Normally on an I2C bus, what ever reads SDA does so on the SCK rising edge.  What ever drives SDA does so on the falling edge of SCK.  In this case the chip is releasing ACK on  SCK falling edge since the ACK period is over with and nobody will be pulling SDA low.  The FPGA should be reading the ACK on SCK rising edge.

  • Thanks for help.In my design,I divide a whole SCLK period to 4 pieces.As a master,FPGA updates the valid data when in the middle of low SCLK to satisfy the slacks of setup-time and hold-time.

    While from slave'view(ADV7181B),it updates SDAT on the both rising and falling edge of SCLK.

    So..I can ignore the ACK value after the falling edge because it's only valid from "rising edge->high->falling edge".