AD8117 Timing Diagram, Serial Mode

Question

Hello, 
 We are planning to use the AD8117, but would like to know about timing characteristics on the serial mode. 
 Please let me know following some questions. 
 AD8117/AD8118 datasheet Rev.A 
 Page 5 
 On the Table 2. & Figure 2. Timing Diagram, Serial Mode, 
 Q1) /CLK pulse width (t2) is 50ns, but CLK Pulse Separation (t4) is 150ns. 
 Is it true ? If that is true , why is it ? Can't use 50%/50% duty clk cycle ? 
 I think maybe 50ns, t2=t4 ? 
 Q2) /CLK to DATA OUT Valid (t7) is 120ns min. 
 Is it min value ? 
 I think maybe max value ? 
 Thanking you 
 With best regards and wishes

ADIApproved · Accepted Answer

Hello, 
 The minimum clock pulse width of 50 ns and the minimum pulse separation of 150 ns are correct as stated in the data sheet. A clock with high and low levels of at least 150 ns each could be used for 50% duty cycle. 
 Yes, the clock -> valid data out specification of 120 ns should be a maximum, not a minimum. Thank you for pointing out the error. 
 Best regards. 
 --Jonathan

Electronic Design Services - PartnerZone

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AD8117 Timing Diagram, Serial Mode