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AD8117 Timing Diagram, Serial Mode


We are planning to use the AD8117, but would like to know about timing characteristics on the serial mode.

Please let me know following some questions.

AD8117/AD8118 datasheet Rev.A

Page 5

On the Table 2. & Figure 2. Timing Diagram, Serial Mode,

Q1)  /CLK pulse width (t2) is 50ns, but CLK Pulse Separation (t4) is 150ns.

       Is it true ? If that is true , why is it ? Can't use 50%/50% duty clk cycle ?

       I think maybe 50ns, t2=t4 ?

Q2)  /CLK to DATA OUT Valid (t7) is 120ns min.

       Is it min value ?

       I think maybe max value ?

Thanking you

With best regards and wishes