Can "ADV7511W" receive 1920x1080 60Hz interlace video with 8bit, pixel clock 148.5MHz?

Hello,

I have a question about input of ADV7511W.

The customer wants to input 1920x1080 60Hz interlace video (sampling clock 74.25MHz) to ADV7511W with 8bit, pixel clock 148.5MHz.
Can ADV7511W do it?
Please refer Table 4 "Input ID Selection" on HW user guide.
He wants ADV7511W to do it with the Input ID=3 or 4.
But the "Maximum Input Clock" is 82.5 MHz.
Is the 82.5 MHz pixel clock?
Or
Is the 82.5 MHz sampling clock?

Thank you.
Best regards.

  • 0
    •  Analog Employees 
    on Dec 16, 2013 7:15 PM

    The 82.5MHz clocks is for DDR inputs.  Normally it is easier to just to use the SDR 74.25 MHz input formats

  • Hello,

    Thank you for your reply.

    Questoin 1:
    What we want to know is whether ADV7511W can receive 1920x1080 60Hz Interlace video (sampling clock 74.25MHz) with "8bit", pixel clock "148.5MHz".
    Can ADV7511W do it?

    Questoin 2:
    The 82.5 MHz is pixel clock, isn't it?

    Thank you.
    Best regards.

  • 0
    •  Analog Employees 
    on Dec 17, 2013 6:39 PM

    1) 1920 x 1080 @ 60 is CEA861 VIC 5.  In theory the device should be able to handle 1920x1080i60 422 over an 8 bit input bus running at 148.5MHz.  I would run it with separate syncs, not embedded syncs.  Note that this has not been verified.

    2)   The 82.5MHz is the maximum DDR clock that can be used.  It is not related to question #1.  In DDR mode 422 over 8 bit bus it is the pixel rate.

  • Hello,

    Thank you very much for your reply.

    About question #1, I understand the device can handle 1920x1080i60 with "8bit", pixel clock "148.5MHz".
    Could you tell me how we should set register settings for that?

    Thank you.
    Best regards.

  • 0
    •  Analog Employees 
    on Dec 18, 2013 8:05 PM

    I would set it up as a standard 1080p transmitter and use separate sycns.  This format has not been tested.

    This sets it up for YCbCr 444 on the input and YCbCr output.

    This configuration also requires DE

    72 01 00 ; Set N Value(6144)

    72 02 18 ; Set N Value(6144)

    72 03 00 ; Set N Value(6144)

    72 15 00 ; 24-bit, 444 YPrPb input

    72 16 60 ; YPrPb 444

    72 17 00 ;

    72 18 46 ; CSC disabled

    72 40 80 ; General Control packet enable

    72 41 10 ; Power down control

    72 48 08 ; Data right justified

    72 49 A8 ; Set Dither_mode - 12-to-10 bit

    72 4C 00 ; 8 bit Output

    72 55 40 ; Set YCrCb 444 in AVinfo Frame

    72 56 08 ; Set active format Aspect

    72 96 20 ; HPD Interrupt clear

    72 98 03 ; ADI Recommended Write

    72 99 02 ; ADI Recommended Write

    72 9C 30 ; PLL Filter R1 Value

    72 9D 61 ; Set clock divide

    72 A2 A4 ; ADI Recommended Write

    72 A3 A4 ; ADI Recommended Write

    72 A5 44 ; ADI Recommended Write

    72 AB 40 ; ADI Recommended Write

    72 AF 16 ; Set HDMI Mode

    72 BA A0 ; Adjust clock delay

    72 D1 FF ; ADI Recommended Write

    72 DE 9C ; ADI Recommended Write

    72 E4 60 ; VCO_Swing_Reference_Voltage