ADV7393 ED TEST BAR

I havn't ,

I use my own board for ADV7393,

I think there is not issue for the hardware ,becasue the SD video  is sucessful(PAL) ,

when I use the 'ED' pattern ,the test bar is error.

so I can be sure  the ' Rset' pin is  510 ohm ,

and DAC1 pulldown resistor is 75ohm .

how you solved this??

Hi,

ADV739x are able to internally generate ED/HD color bar, black bar, and hatch test patterns.

For ED test patterns, a 27 MHz clock signal must be applied to the CLKIN pin.

For HD test patterns, a 74.25 MHz clock signal must be applied to the CLKIN pin.
To generate an ED black bar test pattern, the settings shown in Table62 should be used with an additional write of 0x24 to Sub-address 0x02.Please refer Page79 in adv739x datasheet.

Thanks,

Poornima

Hi,

I am using ADV7391.

i am not getting any ntsc test pattern by using this settings. Can you please guide me.

For ED test patterns, a 27 MHz clock signal  applied to the CLKIN pin

0x00     ->     0x1c 

0x01    ->     0x10

0x31    ->     0x05

0x02    ->     0x24

Hi,

To generate an SD NTSC black bar test pattern, the settings shown in Table 60 should be used with an additional write of 0x24 to Sub-address 0x02

For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9 should be written to Sub-address 0x82.
For component RGB output rather than YPrPb output, 0 should be written to Sub-address 0x02, Bit 5.

Note:For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1), May i know your input format ?

Thanks,

Poornima

Hi,

To generate an SD NTSC black bar test pattern, the settings shown in Table 60 should be used with an additional write of 0x24 to Sub-address 0x02

For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9 should be written to Sub-address 0x82.
For component RGB output rather than YPrPb output, 0 should be written to Sub-address 0x02, Bit 5.

Note:For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1), May i know your input format ?

Thanks,

Poornima

Hi,

I am using ADV7391.

I am getting SD NTSC black bar test pattern but i am not getting ED black bar test pattern 525P.

I am using these settings to generate ED test pattern

For ED test patterns, a 27 MHz clock signal  applied to the CLKIN pin

0x00     ->     0x1c 

0x01    ->     0x10

0x31    ->     0x05

0x02    ->     0x24

Thanks.

Hi Poornima,

Any hardware changes required to generate ED test pattern. I am able to get SD test pattern.

Thanks.

Hi,

Please cross check with reference schematic which is available at ez.analog.com/.../adv739x-design-support-files

And also ED/HD test pattern color controls,three 8-bit registers at Subaddress 0x36 to Subaddress 0x38 are used to program the output color of the internal ED/HD test pattern generator(Subaddress 0x31, Bit 2 = 1), whether it be the lines of the crosshatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input.Please refer Page55 in ADV739x datasheet.

Thanks,

Poornima

Hi Poornima,

Please find attached cross hatch test pattern output.

For ED test patterns, a 27 MHz clock signal  applied to the CLKIN pin

0x00     ->     0x1c 

0x01    ->     0x10

0x31    ->     0x05

0x36  Reg  Value -> 0xA0 (Y value)

0x36  Reg  Value -> 0x51 (Y value)

0x36  Reg  Value -> 0x10 (Y value)

-> Cr value for all 0x80

-> cb value for all 0x80

-> I have connected only Y output to TV.  I have not connected Pr and Pb output to TV.

-> There is vertical black screen in the center of the test pattern. Can you please tell is this correct output ? 

-> If i connect Y output to other TV then i am not getting test pattern video. 

-> I have tried four different TV, I got attached test pattern on one TV only and that also not correct as per my understanding.  

Hi,

  Yes,vertical black screen in the center for hatch test pattern.

  For black color test pattern,Y value should configure as 16(0x10),Cr as 128(0x80),Cb as 128(0x80) as per the table above.May i know the reason,why you have chosen Y value as 0x51,0xA0?

Note: ADV739x does not support color bars in ED/HD resolution. Hatch, black bar and flat field test patterns are supported. That is an error in the data sheet that will be rectified in the next revision of the document.

    Color  bars are just available on SD standards. On ED/HD the user can select between a  black and white bar, a hatch pattern, and a plain color. On the last two, the  color which defines the hatch pattern or the plain frame, can be selected  through registers 0x36-0x39

Thanks,

Poornima

Hi Poornima,

Thanks for your quick response. 

I have used different Y value to check intensity of hatch cross bar (white color lines). I have shared three images of hatch cross-bar pattern(1st  with Y-0x51 , 2nd with Y-0x51 and 3rd with Y-0x10) in previous reply.

-> I tried following settings for Black bar pattern

ED 525P  CLKIN = 27Mhz

ADDR          DATA

0x00     ->     0x1c 

0x01    ->     0x10

0x31    ->     0x05

0x02    ->     0x24

-> I tried with different Tv. One Tv gives me black bar pattern as shown below image. In another one I am getting no video signal detected. I think something is not right. Can you please guide me.

-> I tried following settings for flat field test pattern

ADDR          DATA

0x00     ->     0x1c 

0x01    ->     0x10

0x31    ->     0x0D

Hi,

 For no video case, check Tv info, whether that sink(TV) may support your input format.

Thanks,

Poornima

Hi,

TV is supporting NTSC 525p format. I am not sure but I think issue is with ADV analog output. I have tried with four differenet TV.  

Hi,

 I think,we have tried maximum possibilities case.Do you have one of our evaluation board for ADV7393?

 Please crosscheck with reference schematic which is available at https://ez.analog.com/video/w/documents/801/adv739x-design-support-files

Thanks,

Poornima

Hi,

I am using ADV7391. I don't have any evaluation board. I will check the schematic and get back to you. Thanks for your support.