ADV7393
Recommended for New Designs
The ADV7390Â /Â ADV7391Â /Â ADV7392Â / ADV7393Â are a family of high speed, digital-to-analog video encoders on single monolithic chips. Three 2.7 V/3...
Datasheet
ADV7393 on Analog.com
hello,
I have a question about the test pattern of the ED.
so, I want to generate a test black bar with YPBPR ,I set the register
0x00 -> 0x1c
0x01 -> 0x10
0x31 -> 0x05
0x02 -> 0x24
nothing on the screen,
and I set the NTSC test black bar
0x00 -> 0x1c
0x82 -> 0xc9
0x84 -> 0x40
it is sucessfull
are there some differents about ED and SD in the hardware ?
the DAC1 wave of 'SD'
the DAC1 WAVE of 'ED'
Hi,
I have moved this from the SHARC Processors Community to the Video Community.
Please continue your discussion here.
Thanks,
Colin
Do you have our evaluation board for ADV7393?
-Matt
I havn't ,
I use my own board for ADV7393,
I think there is not issue for the hardware ,becasue the SD video is sucessful(PAL) ,
when I use the 'ED' pattern ,the test bar is error.
so I can be sure the ' Rset' pin is 510 ohm ,
and DAC1 pulldown resistor is 75ohm .
how you solved this??
Hi,
ADV739x are able to internally generate ED/HD color bar, black bar, and hatch test patterns.
For ED test patterns, a 27 MHz clock signal must be applied to the CLKIN pin.
For HD test patterns, a 74.25 MHz clock signal must be applied to the CLKIN pin.
To generate an ED black bar test pattern, the settings shown in Table62 should be used with an additional write of 0x24 to Sub-address 0x02.Please refer Page79 in adv739x datasheet.
Thanks,
Poornima
Hi,
I am using ADV7391.
i am not getting any ntsc test pattern by using this settings. Can you please guide me.
For ED test patterns, a 27 MHz clock signal applied to the CLKIN pin
0x00 -> 0x1c
0x01 -> 0x10
0x31 -> 0x05
0x02 -> 0x24
Hi,
To generate an SD NTSC black bar test pattern, the settings shown in Table 60 should be used with an additional write of 0x24 to Sub-address 0x02
For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9 should be written to Sub-address 0x82.
For component RGB output rather than YPrPb output, 0 should be written to Sub-address 0x02, Bit 5.
Note:For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1), May i know your input format ?
Thanks,
Poornima
Hi,
I am using ADV7391.
I am getting SD NTSC black bar test pattern but i am not getting ED black bar test pattern 525P.
I am using these settings to generate ED test pattern
For ED test patterns, a 27 MHz clock signal applied to the CLKIN pin
0x00 -> 0x1c
0x01 -> 0x10
0x31 -> 0x05
0x02 -> 0x24
Thanks.