I'm trying to generate a PAL SD signal using the ADV7391. The input comes from a camera in BT.601/656 format. I'm using only one DAC (register 0x00 = 0x10) in CVBS mode (reg 0x82 = 0xC3). So I'm expecting a signal according to the BT.470 standard (other registers: 0x80 = 0x11, 0x8C-0x8F according to frequency).
When generating the color bars test pattern everything works fine and the signal looks like BT.470. But when using the camera signal, the output signal is not correct. The time between the EAV and SAV signals according to BT.470 is 12 µs, the line-blanking interval. This consists of 1.5 µs front porch, 4.7 µs sync signal and 5.7 µs back porch. The ADV7391 starts the sync signal immediately when receiving the EAV signal and it's 7.5 µs long instead of 4.7 µs. So the front porch is fully missing and the back porch is too short. The color burst starts correctly around 0.7µs after the end of the sync pulse.
I really tried a lot, but my monitors are always losing the sync. Some monitors do never get a sync. I hope that you have some ideas what's going wrong. How is the timing of front porch/sync/back porch generated?
We are currently looking into your question.
The ADV7391 takes it's timing from the incoming video source, so I suspect there may be an issue there. Can you forward all of the writes you are doing to the part? Could you try setting 0x86 bit  =1, to see if this resolves the issue? If you look at the DAC output on a 'scope, does the video seem to be locked or consistent? What way is 0x86 bit set? Could you try setting this to 0.
Thank you for your answer.
The video signal during the active video is correct. Waving my fingers in front of a white background is visible on the scope. The timing is correct, too: 52 µs active video + 12 µs non active video = 64 µs per line (50 Hz of 312.5 lines). This timing is correctly extracted from the digital video data.
During the non active video the timing is not correct as described above (no front porch, sync signal too long). This cannot be extracted from the digital video signal, because between EAV and SAV (the timing reference signals) there is only constant digital blanking data as described in chapter 2.6 of BT.656-5 (Cr/Cb = 0x80; Y = 0x10).
Setting 0x86 bit 3 to 1 (SD EIA/CEA-861B compliance) doesn't change anything. Bit 6 of 0x86 is set to 0.
The camera gives a 28.375 MHz pixel clock instead of 27 MHz, but this shouldn't be a big deal (subcarrier frequency 0x8C-0x8F is adjusted accordingly). The camera is the Videology 21K15XDIG (see http://www.videologyinc.com/media/products/application%20notes/APN-2XK1XXDIG.pdf). According to this Videology datasheet this works with ADV7174/9. We thought it would work with 7391, too.
Current Configuration (with 0x84 set to 0x30 to disable color for testing, but also tested with color):
reg 0x17 = 0x02 // reset
reg 0x00 = 0x10
reg 0x80 = 0x11
reg 0x82 = 0xC3
reg 0x8C = 0xC8 // adjusted subcarrier frequency
reg 0x8D = 0x0E
reg 0x8E = 0x00
reg 0x8F = 0x28
reg 0x84 = 0x30 // disable color
reg 0x86 = 0x0A // as suggested
I think the issue is with the input clock frequency of 28MHz, the encoders (including the ADV7174) only support a 27MHz input.
did you get your camera to work with the ADV7391 and 28.375 MHz input clock? I'm facing the same issue here.