cp_vid_std[7:0] (IO Map, Address 0x05[7:0]) of ADV7480.

Hello,

I have questions about register cp_vid_std[7:0] (IO Map, Address 0x05[7:0]) of ADV7480.

We think we don't have to change cp_vid_std according to HDMI input resolution.

Your S/W driver(SRC-Rel1.5.0_BETA) seems to set cp_vid_std to "0x53" (720p) fixed.
Even if HDMI input resolution is changed, cp_vid_std is not changed.

Meanwhile, there are example descriptions about cp_vid_std, de_h_start and de_h_end
on ADV748x_Recommended_Settings document page 11 and 12 as follows:

Example 1: cp_vid_std[7:0] = 0x53 (720p), 0x54 (1080i) or 0x5E (1080p). Video input is 720p with Hsync width of 40 pixel clock cycles
Example 2: cp_vid_std[7:0] = 0x53 (720p), 0x54 (1080i) or 0x5E (1080p). Video input is 1080i with Hsync width of 44 pixel clock cycles
Example 3: cp_vid_std[7:0] = 0x53 (720p), 0x54 (1080i) or 0x5E (1080p). Video input is 1080p with Hsync width of 44 pixel clock cycles
Example 4: cp_vid_std[7:0] = 0x53 (720p), 0x54 (1080i) or 0x5E (1080p). Video input is 480p with Hsync width of 62 pixel clock cycles

The "cp_vid_std[7:0] is fixed 0x53 (720p) and de_h_start and de_h_end are changed appropriately" looks like your recommendation.

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Question 1:
  Do you recommend cp_vid_std[7:0] = 0x53 (720p) fixed?

Question 2:
  HDMI must support VGA (640x480).
  When HDMI VGA input to ADV7480 and cp_vid_std[7:0] is fixed 0x53 (720p),
  how should we set de_h_start and de_h_end?
  There are no example description when video input is VGA, so we don't know the register value and sequence.

------------------------------------------------------------------------------------------

Thank you!
Best regards.

  • 0
    •  Analog Employees 
    on Jun 9, 2015 2:17 AM

    Does the customer have one of our ADV7480 evaluation boards?

    -Matt

  • Hello,

    Thank you for your reply.

    The customer doesn't have ADV7480 evaluation board, but I have it.
    So I can confirm the register value of de_h_start and de_h_end when HDMI VGA input to ADV7480 and cp_vid_std[7:0] is fixed 0x53 (720p).
    But I don't know the sequence.
    (There are description about "the sequence of the writes is important and must be followed" on ADV748x_Recommended_Settings document.
    I don't know it.)
    CP Map
    44 8B ?? de_h_end shifted by -?? pixels
    44 8C ?? de_h_end shifted by -?? pixels
    44 8B ?? de_h_start shifted by -?? pixels
    44 8D ?? de_h_start shifted by -?? pixels

    Question 1:
      Do you recommend cp_vid_std[7:0] = 0x53 (720p) fixed?

    Question 2:
      HDMI must support VGA (640x480).
      When HDMI VGA input to ADV7480 and cp_vid_std[7:0] is fixed 0x53 (720p),
      how should we set de_h_start and de_h_end?
      There are no example description when video input is VGA, so we don't know the register value and sequence.

    Thank you!
    Best regards.

  • 0
    •  Analog Employees 
    on Jun 10, 2015 11:58 AM

    Hi,

    Question 1:
      Do you recommend cp_vid_std[7:0] = 0x53 (720p) fixed?

    No, we do not recommend any particular value for CP_VID_STD[7:0]. It depends on the use case. Users can set CP_VID_STD[7:0] to the resolution they want to free run to if they do not want to free run to the video format of the last stable HDMI or MHL input.

    Reminder: The video resolution output by the CP block in free run mode depends on the setting of the dis_auto_param_buff (CP Map, Address 0xC9[0]) control:

    • When dis_auto_param_buff is set to 0b0 (default setting) in HDMI input mode: when free running, the CP block outputs the video format of the last stable HDMI input received, as recorded by the timing parameters buffering block
    • When dis_auto_param_buff is set to 0b0 (default setting) in MHL input mode: if register 0xBA[5:4] in the CP Map is set to value 0b10, the CP block outputs the video format of the last stable MHL input received when free running, as recorded by the timing parameters buffering block. Otherwise the CP block outputs the video format specified by cp_vid_std[7:0] and cp_v_freq[2:0]
    • When dis_auto_param_buff is set to 0b1: when free running, the CP block outputs the video format specified by cp_vid_std[7:0] and cp_v_freq[2:0]

    Question 2:

      HDMI must support VGA (640x480).

      When HDMI VGA input to ADV7480 and cp_vid_std[7:0] is fixed 0x53 (720p),

      how should we set de_h_start and de_h_end?

      There are no example description when video input is VGA, so we don't know the register value and sequence.

    As described in the Recommended Settings Document, when CP_VID_STD[7:0] is set to 0x53 (720p), 0x54 (1080i) or 0x5E (1080p), the picture gets shifted by a number of clocks equal to the hsync width. For example, the hsync width is 40 clock cycles for 720p, so the picture would get shifted by 40 pixel clocks.

    If you look at the CEA-861 specification, you will see that the 640x480p @ 59.94/60Hz has an hsync width of 96 clock cycles.

    The DE sync leading and trailing edges must therefore be shifted by 96 pixels towards the left, i.e.:

    • de_h_start[9:0] = 0x3A0 (-96 pixels of shift)

    • de_h_end[9:0] = 0x3A0 (-96 pixels of shift)

    This results in the following settings (the sequence of the writes is important and must be followed):

    44 8B 43; de_h_end shifted by -96 pixels

    44 8C A0; de_h_end shifted by -96 pixels

    44 8B 4F; de_h_start shifted by -96 pixels

    44 8D A0; de_h_start shifted by -96 pixels

    Best regards

  • Hi XavE-san,

    My questions are all cleared.
    Thank you very much!

    Best regards.