How to implement a dual link DVI receiver by ADV7842?

Question

Hi, 
 ADV7842 can only receive single link DVI signals.So how to implement a dual link DVI receiver by ADV7842? 
 Here's a rough idea:We use two adv7842 to receive DVI Link 1 data and DVI Link 2 data separately.The DVI CLK can be sent to the two adv7842 at the same time.Then we can synchronize two sets of data into one clock domain using two FIFOs in the FPGA,as you can see from the picture below. 
 But how to deal with two HPD signals?And is this idea practicable? 
 
 Regards, 
 Martin

FormerMember · Accepted Answer

This is the way you have to handle dual link DVI using a couple of ADV7842. The rising edge of HPD signals the source to read the EDID. ADV7842 #1 could handle all the HDP and EDID transactions or you could use a discrete EDID EEPROM and let the FPGA control the HPD signal.)

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How to implement a dual link DVI receiver by ADV7842?