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ADV7280 Not Recommended for New Designs
The ADV7280 / ADV7280-M are versatile one-chip, multiformat video decoders. The ADV7280 / ADV7280-M automatically detect standard analog baseband video...
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ADV7280 frame timing on the digital output video bus



		

			

									
					    ADIApproved
					
							

			
				
									
											
			
			
				
  •  Analog Employees  

			
			
			    	
			                    
                
				                on Jun 10, 2016 
				
			
			
		


				
		

		    		    
		    
		    	
			
It appears the ADV7280 has the following frame timing on the digital output video bus when using one of the one of the interlaced CVBS to progressive configuration scripts (“I2P_NTSC_In_Ain1_YPrPb_Out_480p_EAV_SAV.py”).

 

  

   
    

     
Horizontal Active Video

     
720 (1440)

     
Pixels (data clock cycles)

    

    

     
Horizontal blanking

     
138 (276)

     
Pixels (data clock cycles), & includes 8 clocks for SAV and EAV codes per line

    

    

     
Vertical Active Video

     
507

     
Rows**

    

    

     
Vertical Blanking Video

     
18

     
Rows**

    

    

     
Data bus clock frequency

     
~54

     
MHz

    

   
  

 

 
**Because of the way EAV and SAV BT.656 codes are swapped around for vertical blanking, its hard to tell if this is correct or if it should be interpreted instead as 508 active lines and 17 blanking lines.

 
Can you confirm what the correct active video and blanking intervals are for the digital output video frame?

 
Additionally:

 
    
  
  1. The output clock period seems to jitter a fair amount. Is there a min/max clock period expected for this bus clock?
    2. 
  
  2. It appears that the BT.656 codes for the vertical blanking interval may have swapped EAV and SAV ordering. 
    3. 
 

 
Is that accurate? 

 
Or do I potentially have something configured incorrectly in the ADV7280?

 
The ADV7280 pattern appears to be:

 
    
  
  1. For line 1-506 active video: SAV (0x80) à 720 active pixels à EAV (0x9D) à 134 pixels à repeating until finish line 506
    2. 
  
  2. Line 507 active video: SAV (0x80) à 720 active pixels à followed by:
    3. 
  
  3. Line 1-18 vertical blanking: “SAV+vertical blanking w/wrong ECC?” (0xAE) à 134 pixels à “EAV+vertical blanking w/wrong ECC?” (0xB3) à 720 pixels à repeating until finish 18th blanking line then…
    4. 
  
  4. Line 1 active video lead-in of:  EAV (0x9D) à 134 pixels à hop to line 1 active video start
    5. 
 

 
While I was expecting something without the flipping SAV/EAV parameters for vertical blanking lines, e.g.:

 
    
  
  1. Lines 1-507 active video: SAV (0x80) à 720 active pixels à EAV (0x9D) à 134 pixels à repeating until finish line 507
    2. 
  
  2. Line 1-18 vertical blanking: “SAV+vertical blanking” (0xAB) à 720 vertical blanking pixels à “EAV+vertical blanking” (0xB6) à 134 pixels à return to line 1 active video.
    3. 
  
  3. Vertical blanking codes seem to have the wrong ECC bits in the lower nibble from what I was expecting.
    4. 
 

 
SAV+vertical blanking = 0xAE from ADV7280, but isn’t spec 0xAB?

 
EAV+vertical blanking = 0xB3 from ADV7280, but isn’t spec 0xB6?

 
    
  
  1. The “Boundary Box” test pattern output doesn’t appear to be working correctly in this operating mode.
    2. 
 

 
It is specified as follows:

 
But in the operating mode we’re using, it does not draw a box of that description on the BT.656 digital video bus.

 
FYI, I enabled the test mode by changing these bits in the devkit GUI:

 
For the digital video output’s 720x507 frame, I see:

 
    
  
  • A solid white vertical line in columns 1 and 2
    • 
  
  • A solid ‘gray’ vertical line column 3 
    • 
  
  • A solid ‘gray’ vertical line column 720 and somewhere mid-frame this transitions to from a brighter to a darker gray in the code values
    • 
  
  • A solid white horizontal line in row 1
    • 
  
  • A solid ‘gray’ horizontal line in row 2
    • 
  
  • And no apparent bottom horizontal line
    • 
 

 
Does this only work correctly in one of the other operating modes? 

									
			        
		


				
						
        

    
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                 adv7280 frame_timing digital_output_video_ bus*
                
                                                    
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													0
							
			
				
									
							        
			
			
			
    •  Analog Employees  
    
            
			                            
                                                                                                                        
            
				
			
            
					
    
	
    

		
		
    
					
    Dear Sir/Madam,
    
 
    0) Could you try using an interlaced script first. You are currently using a progressive script. The interlaced-to-progressive converter in the ADV7280 works by interpolating between line to generate the missing lines (e.g. interpolating between lines 1 and 3 to generate line 2). 
    
 
    1) The ADV7280 was evaluated and found to be fully compliant with the ITU-R BT.656-3 and ITU-R BT.656-4 specifications. These specifications can be found here: http://www.itu.int/rec/R-REC-BT.656/en
    
 
    2) By default the ADV7280 outputs according to the ITU-R BT.656-3 specification. There are 10 extra blanking lines in the vertical blanking period for NTSC signals in ITU-R BT.656-3 mode compared to ITU-R BT.656-4 mode.
    
 
    3) You can switch between the ITU-R BT.656-3 mode and  ITU-R BT.656-4 output mode by toggling the User Map register 0x04 bit [7].
    
 
         0: (default) BT656-3 mode
    
 
         1: BT656-4 mode
    
 
    4) The line lock clock output (LLC) from the ADV7280 has a nominal frequency of 27 MHz. However this clock is locked to the length of the horizontal line length of the incomming analog video signal. If horizontal line length is too long/short the LLC frequency will speed up/down to compensate. The LLC clock can vary by +/- 5%. See table 5 of ADV7280 datasheet (Rev.A).
    
 
    5)  Post on how to modify the boundary box test pattern is here:
    
 
    boundary box test pattern can't  be complete display 
    
 
    In interlaced mode the boundary box test pattern top line appears on odd fields and bottom line appears on even fields. 
    
 
    In interlaced mode the first/last pixel on every second line in the odd and even fields are white to generate the white vertical lines.
    
 
    In progressive mode the line interpolation algorithm doubles the size of the odd and even fields. Therefore the first frame could be doubled odd field that will only have the white line at its top. The next frame could be doubled even field that will only have the white line at its bottom.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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													0
							
			
				
									
							        
			
			
			
    •  Analog Employees  
    
            
			                            
                                                                                                                        
            
				
			
            
					
    
	
    

		
		
    
					
    Dear Sir/Madam,
    
 
    0) Could you try using an interlaced script first. You are currently using a progressive script. The interlaced-to-progressive converter in the ADV7280 works by interpolating between line to generate the missing lines (e.g. interpolating between lines 1 and 3 to generate line 2). 
    
 
    1) The ADV7280 was evaluated and found to be fully compliant with the ITU-R BT.656-3 and ITU-R BT.656-4 specifications. These specifications can be found here: http://www.itu.int/rec/R-REC-BT.656/en
    
 
    2) By default the ADV7280 outputs according to the ITU-R BT.656-3 specification. There are 10 extra blanking lines in the vertical blanking period for NTSC signals in ITU-R BT.656-3 mode compared to ITU-R BT.656-4 mode.
    
 
    3) You can switch between the ITU-R BT.656-3 mode and  ITU-R BT.656-4 output mode by toggling the User Map register 0x04 bit [7].
    
 
         0: (default) BT656-3 mode
    
 
         1: BT656-4 mode
    
 
    4) The line lock clock output (LLC) from the ADV7280 has a nominal frequency of 27 MHz. However this clock is locked to the length of the horizontal line length of the incomming analog video signal. If horizontal line length is too long/short the LLC frequency will speed up/down to compensate. The LLC clock can vary by +/- 5%. See table 5 of ADV7280 datasheet (Rev.A).
    
 
    5)  Post on how to modify the boundary box test pattern is here:
    
 
    boundary box test pattern can't  be complete display 
    
 
    In interlaced mode the boundary box test pattern top line appears on odd fields and bottom line appears on even fields. 
    
 
    In interlaced mode the first/last pixel on every second line in the odd and even fields are white to generate the white vertical lines.
    
 
    In progressive mode the line interpolation algorithm doubles the size of the odd and even fields. Therefore the first frame could be doubled odd field that will only have the white line at its top. The next frame could be doubled even field that will only have the white line at its bottom.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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