I've seen the message: Using ADV7393 as black burst generator
I want to do the same, I'm using slave SD Timing Mode 1 (using HSYNC and Field), connected a 27Mhz clk and left the pixel data P[7:0] connected to GND.
But i have a problem getting the analog video output to frame align on the sync inputs. It is locked to the pulses but it starts random not locked to the Field. I've tried reseting the internal SD timing from the ADV7393 by setting bit7 from register 0x8A.
But then it randomly starts with its frame
All of that is correct for active video inputs, but the internal test patterns use only use the external clock and not the sync signals. The internal test patterns were designed to verify operation of the encoders and rule out issues with the external timing.