Post Go back to editing

ADV7610: Removing vertical blanking period completely

Thread Summary

The user is experiencing a 20-pixel vertical shift in the YCbCr 16-bit video stream from an ADV7610, caused by the processor ignoring the low data enable pin. The final answer indicates that the padding is set by the source and EDID, and the ADV7610 cannot reduce the vertical blanking period beyond the ±7 pixel adjustment in the START_VS register. The engineer suggests checking Figure 52 in the ADV7612 hardware manual for output synchronization signal positioning.
AI Generated Content


Hello,

I've connected an ADV7610 to a 720p video source. It is sending out a very nice YCbCr 16 bit stream to a processor, that is being captured relatively well. Video is fine, it's just shifted to the bottom of 20 pixels. Those 20 pixels are the vertical blanking period: the processor receiving the YCbCr input is ignoring the low data enable pin (that is working correctly), so data is saved starting from the blanking period (that I checked with a scope is indeed 20 lines).

I've tried to change the START_VS register, that allows for a reduction in the vertical blanking period, but I cannot reduce it to zero since that the adjustment is limited to +- 7 pixels.

Is there any other way to reduce or eliminate the vertical blanking period?

Thank You.

  • Hi,

    Do you have one of our evaluation boards for ADV7610/ADV7611/ADV7612 as reference?  How do you configure the board either through script or through software?

    Did you try the same test in one of our evaluation board and observe the same behavior?

    Best Regards,

    Jeyasudha.M

  • Does the padding depend on the HDMI input values? So that they depend on what is set in the EDID? I think we can all agree this problem has nothing to do with hardware, I'm just asking if apart from that register there are other ways to decrease timing between h/v sync and data, it's that simple.

  • FormerMember
    FormerMember
on Jul 26, 2016 3:02 PM
0

The padding is really set by the source and how it interprets the EDID.  You cannot really decrease the timing since this would change the format which the ADV7610 cannot do.

You change the output synchronization signal positioning a bit but the overall timing must stay the same.  Check out Figure 52 in the ADV7612 hardware manual.