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TMDS clock output frequency of ADV7511W.

Hello,

I have some questions about TMDS clock output frequency of ADV7511W.

My customer uses ADV7511W on their system.
When HDMI cable is connected to the system, he can see incorrect frequency on the TMDS clock temporarily
while / after the registers are set for the ADV7511W. After a short time, the frequency becomes correct.
I tried this on evaluation board (ADV748x Eval board) with script files.
I can see the same phenomenon when the script is first written.
=>Generally, HDMI cable is connected, then CPU writes the registers of ADV7511.
  But S/W driver is not implemented to our ADV748x Eval board, so I confirmed the TMDS waveform when the script is first written.

I described the waveforms and our questions in attached file.
Please see the file "ADV7511W_TMDS_CLK.xlsx".

Thank you!
Best regards.

ADV7511W_TMDS_CLK.xlsx
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  • Hi Tamu,

    The designers expect the PLL lock time to be in the order of tens of milliseconds up to a couple of video frames.

    There is a gears and such that the PLLs can select in order to be in the correct lock/acquire range. All in all this process is expected to take only a few video frames at most.

    At 60Hz refresh that would be 16ms per video frame. So a wait time of 110ms is approx 6 video frames at a 60Hz refresh.

    Unless the input was of very bad quality (ie. jittery, bad signal integrity) then 110ms is seen by our designers as an ample time to wait to allow the PLL to lock under normal circumstances.

    I hope this helps ?

    Mike

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  • Hi Tamu,

    The designers expect the PLL lock time to be in the order of tens of milliseconds up to a couple of video frames.

    There is a gears and such that the PLLs can select in order to be in the correct lock/acquire range. All in all this process is expected to take only a few video frames at most.

    At 60Hz refresh that would be 16ms per video frame. So a wait time of 110ms is approx 6 video frames at a 60Hz refresh.

    Unless the input was of very bad quality (ie. jittery, bad signal integrity) then 110ms is seen by our designers as an ample time to wait to allow the PLL to lock under normal circumstances.

    I hope this helps ?

    Mike

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