Hey folks,
I'm using the ADV7341 as an SD analog video encoder (CVBS + Y/C outputs, NTSC). It is fed YCbCr 4:2:2 (BT.656-style) video from an external video processor/ISP, which downscales a 1080p sensor image to standard definition. The ADV7341 runs in slave timing mode.
The output is largely working: the NTSC image locks and looks correct across almost the entire frame. However, there is a persistent vertical "stretching"/distortion confined to the bottom band of the image — the rest of the frame is fine, and only the lower portion appears vertically stretched (not noise or tearing). I've attached a short capture of the live feed.
Our current ADV7341 register configuration (key registers):
- 0x80 (SD Mode Reg 1) = 0x10 — NTSC standard
- 0x82 (SD Mode Reg 2) = 0xC9 — pixel data valid, CVBS + Y/C output, SSAF filters, pedestal enabled
- 0x86 (SD Mode Reg 5) = 0x82 — subcarrier adjust + RGB color reversal
- 0x87 (SD Mode Reg 6) = 0x20 — SD input standard auto-detect, YCbCr input
- 0x88 (SD Mode Reg 7) = 0x10 — input bit width
- 0x8A (SD Timing Reg 0) = 0x08 — slave mode, SD timing mode 0
What we have checked:
- Horizontal timing is good and the image is otherwise stable and locked.
- The distortion is only at the bottom and looks like vertical stretching rather than noise or tearing.
- We suspect the source may be delivering a slightly short vertical active-line count, so the bottom appears stretched to fill the frame — but we want to understand the ADV7341 side before concluding that.
Questions:
1. In slave timing mode, how does the ADV7341 handle an input whose vertical active-line count is slightly short of (or different from) the NTSC standard? Does the encoder stretch/replicate the last lines, or would this always be an upstream (source) issue?
2. Which timing-mode/sync settings (e.g. SD Timing Reg 0x8A, HSYNC/VSYNC vs. EAV/SAV embedded sync) are most relevant to correct vertical active placement?
3. Is there any register setting to blank or constrain the bottom lines, or to enforce the NTSC vertical active window regardless of the input?
4. Can you confirm the recommended register configuration for BT.656 / YCbCr 4:2:2 SD input with NTSC output?
Any pointers would be greatly appreciated. Thank you!
