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ADV7513 Recommended for New Designs
The ADV7513 is a 165 MHz, High-Definition Multimedia Interface (HDMI®) transmitter that is ideal for DVD players/ recorders, digital set-top boxes, A...
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ADV7513 Input Pixel Clock Jitter Tolerance

		
	
				

			

									
					    KFEIFujita
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Aug 31, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user inquires about the maximum allowable jitter for the ADV7513 input pixel clock and whether the TMDS differential clock output can meet HDMI 1.4b requirements. The final answer clarifies that the ADV7513 input pixel clock has no specific jitter requirements, only timing constraints, and the TMDS output meets HDMI 1.4b jitter limits. The 0.25 Tbit limit for TMDS differential clock output does not apply to the input pixel clock.
                        	    

                
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The FPGA outputs 24-bit RGB data, pixel clock, HSYNC, VSYNC, and DE signals to the ADV7513.
The FPGA output pixel clock has relatively large period jitter.
We would like to confirm whether the TMDS output can meet the HDMI 1.4b requirements.






Target resolutions
pixel clock [MHz]
pixel clock [ns]
period jitter [ns p-p]
phase jitter [ns p-p]
cycle-to-cycle jitter [ns p-p]




VGA60
25.2
39.683
2.78
0.35
3.17




VGA59.94
25.175
39.722
2.78
0.35
3.18




XGA60
65
15.385
1.08
0.35
1.23




FHD60
148.5
6.734
0.47
0.35
0.54






Q1. Is there a maximum allowable jitter for the ADV7513 input pixel clock?
I reviewed the ADV7513 Hardware User’s Guide, Section 4: Specifications, but could not find an input clock jitter specification.

Q2. With the input jitter values shown in the table, can the TMDS differential clock output meet the HDMI 1.4b jitter requirement?
We are particularly concerned about the period jitter.
If you have any input period jitter test data for HDMI 1.4b compliance, could you please share it along with the test conditions?

			

			
									
		                             
                        

    

                                            
                 hardware
                
                                                    
                 clock jitter
                
                                                    
                 adv7513
                
                                                    
                 fpga
                
                                                    
                 Interface Transmitters
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			








	
	
	
	



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    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Sep 2, 2026 2:33 AM
            
            
						
			            		
    
		
										+1
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

       Please find the below response ,
    

    Q1. In your previous response, does “the jitter should be within the HDMI specification” mean that the allowable jitter limits for the ADV7513 input pixel clock and the TMDS differential output clock are identical?
    

         >> The input pixel clock does not have a specified input clock jitter requirement. As long as the timing requirements are met, it should be fine.
    

              The ADV7513 input pixel bus timing is specified in Figure 2 of the Hardware User Guide.
    

              Kindly note that no input clock jitter is defined or required, as long as the input timing constraints are met. The output TMDS clock jitter meets the HDMI 1.4 specifications, which are defined in terms of Tbit values.
    

    

    Q2. I found that the HDMI 1.4b jitter limit for the TMDS differential clock output is 0.25 Tbit. Does this 0.25 Tbit limit also apply to the period jitter of the ADV7513 input pixel clock as well?
    

            As mentioned, the input pixel clock does not have an input clock jitter specification. As long as you meet the input timing requirements, the input pixel port will work fine.
    

    

    Thanks,
    

    Poornima S
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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Reply

    


  • 
	
    



	
			
		
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Sep 2, 2026 2:33 AM
            
            
						
			            		
    
		
										+1
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

       Please find the below response ,
    

    Q1. In your previous response, does “the jitter should be within the HDMI specification” mean that the allowable jitter limits for the ADV7513 input pixel clock and the TMDS differential output clock are identical?
    

         >> The input pixel clock does not have a specified input clock jitter requirement. As long as the timing requirements are met, it should be fine.
    

              The ADV7513 input pixel bus timing is specified in Figure 2 of the Hardware User Guide.
    

              Kindly note that no input clock jitter is defined or required, as long as the input timing constraints are met. The output TMDS clock jitter meets the HDMI 1.4 specifications, which are defined in terms of Tbit values.
    

    

    Q2. I found that the HDMI 1.4b jitter limit for the TMDS differential clock output is 0.25 Tbit. Does this 0.25 Tbit limit also apply to the period jitter of the ADV7513 input pixel clock as well?
    

            As mentioned, the input pixel clock does not have an input clock jitter specification. As long as you meet the input timing requirements, the input pixel port will work fine.
    

    

    Thanks,
    

    Poornima S
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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