Category: Hardware
We are developing the FPGA-side I2C configuration for an ADV7513, where the output resolution is set according to the EDID of the connected monitor.
Target resolutions: Full HD@60Hz, XGA@60Hz, VGA@60/59.94Hz
The FPGA handles the following:
- ADV7513 initialization
- Monitor connect detection via the HPD signal
- EDID readout after connection
- Resolution setting per the EDID
- ADV7513 reconfiguration on resolution change
- HDMI output stop on disconnection
Q1. Could you advise a recommended control flow for this sequence, and provide any reference sample code for the I2C register settings?
Q2. Below are our initial settings, still in draft, based on the Quick Start guide. Please point out anything missing or unnecessary.
| Offset | Register Name | Value | Note |
|---|---|---|---|
| 0x41 | Power Down Control | 0x10 | Release power-down |
| 0x98 | Fixed Register | 0x03 | Internal analog core driver optimization (fixed) |
| 0x9A | Fixed Register (PLL) | 0xE0 | Internal PLL stabilization (enable high-speed serial clock) |
| 0x9C | Fixed Register | 0x30 | PLL filter / internal timing optimization (fixed) |
| 0x9D | Fixed Register | 0x61 | Clock line drive strength (fixed) |
| 0xA2, 0xA3 | Fixed Register | 0xA4 | Buffer bias adjustment (fixed) |
| 0xE0 | Fixed Register | 0xD0 | Internal state machine initialization |
| 0xF9 | Fixed Register | 0x00 | I2C address conflict prevention |
| 0x3B | Video Identification Code | 0x00 | VIC mode: Auto |
| 0x94 | Interrupt Enable | 0xC0 | Enable HPD interrupt |
| 0x15 | Video Input Format | 0x00 | 24-bit RGB |
| 0x16 | Video Output Format / Input Option | 0x30 | Color Depth: 8-bit |
| 0x17 | Aspect Ratio | 0x02 | Aspect ratio 16:9 |
Thanks.
Regards,
Fujita
Fujita
