Product: MAX96717F serializer + MAX96724 quad deserializer
Mode: GMSL2 pixel mode, 3Gbps link, RAW12 1920x1536@30
Input sensor VC: VC0
Target serializer-side remap: VC2 or VC3
Goal
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Assign distinct standard virtual channels to two identical cameras at the MAX96717F serializer, allowing the MAX96724 to use identity pass-through.
Documentation discrepancy
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The public MAX96717/F/R User Guide contains conflicting register definitions:
Table 10 states:
- 0x0330 bit7 = Ctrl1_vcx_en
- 0x0331 bit5 = Ctrl1_vc_map_en
The following "Extended Virtual Channels Programming Example" instead writes:
- 0x0331 <- 0xB0 for VC extension
- 0x0330 <- 0x20 for VC remapping
- 0x0345 <- 0x50 for VC0 -> VC5
On our MAX96717F device, 0x0330 bit7 does not retain a written 1 and always reads back as 0. The bit locations used by the programming example do accept and retain the written values:
- 0x0331 <- 0xB0
- 0x0330 <- 0x20
- 0x0345 <- 0x30 or 0x20
Please confirm the correct register and bit definitions for MAX96717F and whether Table 10 or the programming example is authoritative.
Observed downstream behavior
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Before the serializer writes, the MAX96724 passes the stream using MAP entries matching source VC0.
After applying the programming-example register locations, the previous source-VC0 MAP configuration no longer produces output, while the MAX96724 video pipe continues to report VIDEO_LOCK. This shows that downstream matching behavior changes, but we have not independently decoded the resulting on-wire VC.
We tested the following MAX96724-side combinations:
- controller 1 csi2_vcx_en enabled: 0x094A = 0xD0
- controller 1 csi2_vcx_en disabled: 0x094A = 0xC0
- MAP entries matching the intended new standard VC (VC2 or VC3), with identity SRC/DST mappings for RAW12, FS and FE
- MAP entries matching the original VC0 as a control
- extended-VC MSB registers for the relevant pipe left at zero because the intended VC is <= 3
All tested combinations produced zero frames at the MIPI output.
Questions
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1. What exact MAX96724 configuration is required to receive a pixel-mode GMSL2 stream remapped by MAX96717F ctrl1_vc_map?
2. When the remap target is a standard VC <= 3, is ctrl1_vcx_en required on the serializer or deserializer?
3. Does enabling ctrl1_vcx_en change the GMSL2 link encoding even for a target VC <= 3?
4. Is there any per-link or per-pipe extended-VC unpack/enable setting on MAX96724 not described in the public User Guide?
5. Please confirm and correct the MAX96717/F/R User Guide discrepancy between Table 10 and the programming example.
We can provide the exact write/readback sequence and full MAX96717F/MAX96724 register dumps if required.
