Products Mentioned

ADV7182A Recommended for New Designs
The ADV7182A has the same pinout and is software compatible with the ADV7182. The ADV7182A is a versatile, one chip, multiformat video decoder that automatically...
Datasheet
ADV7182A on Analog.com

ADV7511 Recommended for New Designs
The ADV7511 is a 225 MHz High-Definition Multimedia Interface (HDMI®) transmitter, which is ideal for home entertainment products including DVD players...
Datasheet
ADV7511 on Analog.com

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ADV7182A 576i stream not being recieved by monitor/tv at the output of an ADV7511 (within a Zedboard)

		
	
				

			

									
					    ArnauVB64
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on May 31, 2026 
				
			
			
		

		
		                     
				
        		

		    
		    		    

		      		            		        
Category: Hardware

    		        		        		    		    

		    		    
		    			

			    


Hi everyone,


 


I developed a board using the ADV7182A which correctly outputs a blue screen when in free run mode and no input (576i/50hz 4:2:2 itu-r bt 656-4 compliant with embedded syncs @ 27MHz) as shown in the picture below. Have tried to configure the ADV7511 to take this input from its pins 19:12 (HD11 to HD4 in the zedboard) and send it right through to several monitors/TVs but none seem to work.


I assume that since my system has a 27MHz clk and the pixel clock is 13.5MHZ, the ADV7511 automatically repeats pixels in order to match the minimum frequency for TMDS. Have tried configuring it in several ways and either VHDL or C code in the PS sent through the FPGA fabric. None have seemed to work, despite trying multiple configurations for it. Here is the latest iteration of the VHDL configuration (each Hex value is in the format [Address][Value]): 


 


 -- Fixed Registers That Must Be Set (Table 14)
        -----------------------------------------------
        x"9803", x"9AE0", x"9C30", x"9D61", x"A2A4", x"A3A4", x"E0D0",
        x"F900",
  
        -----------------
        -- Main Power Up & Sync Adj
        -----------------
        x"4112",


        ---------------------------------------
        -- Input mode 
        ---------------------------------------
        x"1514", -- Input ID: 4 
        x"16B4", -- Output Format
        x"1765", -- VSync and HSync, 4:2:2 to 4:4:4 Up Conversion 
        x"4810",


        ---------------------------------------
        -- Sync extraction
        ---------------------------------------
        
         x"3003", x"3103", x"32F0", x"3308",x"3403",
         x"3520", x"36D6", x"3705", x"38A0",x"3912",x"3A00",
         x"D703", x"D803", x"D9F0", x"DA08",x"DB03",
        
        ---------------
        -- Output mode
        ---------------
        x"AF06" -- HDMI mode


 


 


 


ADV7182A Output captured by an oscilloscope as a parallel clocked signal (the Cb Y Cr Y sequence matches with the default configuration):








  




Would gladly appreciate any insight into which part of the configuration for the ADV 7511 might be the culprit or if my assumptions about the double pixel clock are incorrect. Hope the information provided is sufficient. 




Thanks in advance!


 


Arnau

			

			
									
		                             
                        

    

                                            
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                on Jun 20, 2026 10:22 AM
            
            
						
			            		
    
		
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    Hi,
    

    Sorry for the long time I've taken to reply, the original message did not upload somehow.
    

    Your insight led me to find the culprit of the issue. I had misunderstood/was mislead by the information in the datasheet regarding pixel multiplication. I assumed that clock multiplication was not needed, since my input clock was 27MHz, but sent a whole pixel over 2 clock periods. I assumed I needed 2x pixel repetition, but no clock multiplication at all, since whole pixels could already be sent in a single clock period over HDMI and 27MHz sufficed. 
    

    I take it that the clock being used is not the "input clock" as stated in the datasheet, but the actual pixel clock implicit to the input format. Everything started when i set clk multiplication to 2x.
    

    Thanks for the support,
    

    

    Arnau
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Jun 22, 2026 1:28 AM
            
            
												
						in reply to ArnauVB64
					
										
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

       Thanks for letting us know.
    

    

    Thanks,
    

    Poornima S
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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