ADV7182A 576i stream not being recieved by monitor/tv at the output of an ADV7511 (within a Zedboard)

ArnauVB64 on May 31, 2026

Category: Hardware

Hi everyone,

I developed a board using the ADV7182A which correctly outputs a blue screen when in free run mode and no input (576i/50hz 4:2:2 itu-r bt 656-4 compliant with embedded syncs @ 27MHz) as shown in the picture below. Have tried to configure the ADV7511 to take this input from its pins 19:12 (HD11 to HD4 in the zedboard) and send it right through to several monitors/TVs but none seem to work.

I assume that since my system has a 27MHz clk and the pixel clock is 13.5MHZ, the ADV7511 automatically repeats pixels in order to match the minimum frequency for TMDS. Have tried configuring it in several ways and either VHDL or C code in the PS sent through the FPGA fabric. None have seemed to work, despite trying multiple configurations for it. Here is the latest iteration of the VHDL configuration (each Hex value is in the format [Address][Value]):

-- Fixed Registers That Must Be Set (Table 14)
-----------------------------------------------
x"9803", x"9AE0", x"9C30", x"9D61", x"A2A4", x"A3A4", x"E0D0",
x"F900",

-----------------
-- Main Power Up & Sync Adj
-----------------
x"4112",

---------------------------------------
-- Input mode
---------------------------------------
x"1514", -- Input ID: 4
x"16B4", -- Output Format
x"1765", -- VSync and HSync, 4:2:2 to 4:4:4 Up Conversion
x"4810",

---------------------------------------
-- Sync extraction
---------------------------------------

x"3003", x"3103", x"32F0", x"3308",x"3403",
x"3520", x"36D6", x"3705", x"38A0",x"3912",x"3A00",
x"D703", x"D803", x"D9F0", x"DA08",x"DB03",

---------------
-- Output mode
---------------
x"AF06" -- HDMI mode

ADV7182A Output captured by an oscilloscope as a parallel clocked signal (the Cb Y Cr Y sequence matches with the default configuration):

Would gladly appreciate any insight into which part of the configuration for the ADV 7511 might be the culprit or if my assumptions about the double pixel clock are incorrect. Hope the information provided is sufficient.

Thanks in advance!

Arnau

PoornimaSubramani

on Jun 17, 2026 9:09 AM
0
Hi,

Kindly note that, In the manual pixel repeat selection case, the VIC sent in the AVI info frame will need to be set in register '0x3C'. The multiplication of the input clock must be programmed in 0x3B[6:5], and the pixel repeat value sent to the Rx must be programmed in 0x3B[4:3], Please ensure below registers at your end and let us know at https://www.analog.com/media/en/technical-documentation/evaluation-documentation/ADV7511W-Programming-Guide.pdf

Also readback using register '0x3D' and '0x3F'

Thanks,

Poornima S
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ADV7182A 576i stream not being recieved by monitor/tv at the output of an ADV7511 (within a Zedboard)